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[ | ||
{ | ||
"top": "vexRiscvTest", | ||
"stage": "test", | ||
"targets": "Specific [-1]" | ||
} | ||
] |
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-- SPDX-FileCopyrightText: 2024 Google LLC | ||
-- | ||
-- SPDX-License-Identifier: Apache-2.0 | ||
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{-# LANGUAGE NumericUnderscores #-} | ||
{-# LANGUAGE RecordWildCards #-} | ||
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-- | Logic for extracting memory maps from circuits in this project. | ||
-- This is a separate module from MemoryMaps because of GHC's stage restrictions | ||
-- around TemplateHaskell. | ||
module Bittide.Instances.MemoryMapLogic where | ||
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import Clash.Prelude | ||
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import Control.Monad (forM_) | ||
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import Protocols.MemoryMap ( annotationSnd, MemoryMap ) | ||
import Bittide.Instances.Hitl.VexRiscv (cpuCircuit) | ||
import Protocols.MemoryMap.Check (CheckConfiguration(..), check, MemoryMapValidationErrors(..), shortLocation, prettyPrintPath) | ||
import Project.FilePath (findParentContaining, buildDir) | ||
import System.FilePath | ||
import Language.Haskell.TH (runIO, reportError, Q) | ||
import System.Directory (createDirectoryIfMissing) | ||
import Protocols.MemoryMap.Check.Overlap (OverlapError(..)) | ||
import Protocols.MemoryMap.Check.AbsAddress (AbsAddressValidateError(..)) | ||
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import qualified Data.List as L | ||
import qualified Data.ByteString.Lazy as BS | ||
import Protocols.MemoryMap.Json (memoryMapJson) | ||
import Data.Aeson (encode) | ||
import Text.Printf (printf) | ||
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data MemMapProcessing = MemMapProcessing | ||
{ name :: String | ||
, memMap :: MemoryMap | ||
, checkConfig :: CheckConfiguration | ||
, jsonOutput :: Maybe FilePath | ||
} | ||
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defaultCheckConfig :: CheckConfiguration | ||
defaultCheckConfig = CheckConfiguration | ||
{ startAddr = 0x0000_0000 | ||
, endAddr = 0xFFFF_FFFF | ||
} | ||
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unSimOnly :: SimOnly a -> a | ||
unSimOnly (SimOnly x) = x | ||
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memMaps :: [MemMapProcessing] | ||
memMaps = | ||
[ MemMapProcessing | ||
{ name = "VexRiscv" | ||
, memMap = unSimOnly $ annotationSnd @System cpuCircuit | ||
, checkConfig = defaultCheckConfig | ||
, jsonOutput = Just "vexriscv.json" | ||
} | ||
] | ||
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processMemoryMaps :: Q () | ||
processMemoryMaps = do | ||
memMapDir <- runIO $ do | ||
root <- findParentContaining "cabal.project" | ||
let dir = root </> buildDir </> "memory_maps" | ||
createDirectoryIfMissing True dir | ||
pure dir | ||
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forM_ memMaps $ \(MemMapProcessing{..}) -> do | ||
case check checkConfig memMap of | ||
Left MemoryMapValidationErrors{..} -> do | ||
let absErrorMsgs = flip L.map absAddrErrors $ \AbsAddressValidateError{..} -> | ||
let path' = prettyPrintPath path | ||
component = case componentName of | ||
Just name' -> name' | ||
Nothing -> "interconnect " <> path' | ||
in | ||
printf "Expected component %s at %08X but found %08X (%s)" component expected got (shortLocation location) | ||
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let overlapErrorMsgs = flip L.map overlapErrors $ \case | ||
OverlapError{..} -> | ||
printf "Component %s (%08X + %08X) overlaps with %s at address (%08X) (%s)" | ||
(prettyPrintPath path) startAddr componentSize | ||
(prettyPrintPath overlapsWith) overlapsAt | ||
(shortLocation location) | ||
SizeExceedsError{..} -> | ||
printf "Component %s (%08X + %08X) exceeds available size %08X (%s)" | ||
(prettyPrintPath path) startAddr requestedSize | ||
availableSize | ||
(shortLocation location) | ||
reportError (unlines $ absErrorMsgs <> overlapErrorMsgs) | ||
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Right checkedMemMap -> do | ||
case jsonOutput of | ||
Nothing -> pure () | ||
Just path -> do | ||
let json = memoryMapJson checkedMemMap | ||
runIO $ BS.writeFile (memMapDir </> path) (encode json) | ||
pure () | ||
pure () |
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-- SPDX-FileCopyrightText: 2024 Google LLC | ||
-- | ||
-- SPDX-License-Identifier: Apache-2.0 | ||
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{-# LANGUAGE NumericUnderscores #-} | ||
{-# LANGUAGE RecordWildCards #-} | ||
module Bittide.Instances.MemoryMaps where | ||
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import Clash.Prelude | ||
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import Bittide.Instances.MemoryMapLogic (processMemoryMaps) | ||
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$(do | ||
processMemoryMaps | ||
pure []) |
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