add circuit versions of scatter- and gatherUnit

bittide/src/Bittide/Node.hs

@@ -175,6 +175,34 @@ gppe (GppeConfig linkConfig peConfig, linkIn, splitAtI -> (nmuM2S0, nmuM2S1)) =
   nmuS2Ms = suS2M :> guS2M :> Nil
   sc = sequenceCounter
 
+gppeM ::
+  (KnownNat nmuRemBusWidth, 2 <= nmuRemBusWidth, HiddenClockResetEnable dom) =>
+  -- |
+  -- ( Configures all local parameters
+  -- , Incoming 'Bittide.Link'
+  -- , Incoming @Vector@ of master busses
+  -- )
+  ( GppeConfig nmuRemBusWidth
+  , Signal dom (DataLink 64)
+  , Vec 4 (Signal dom (WishboneM2S nmuRemBusWidth 4 (Bytes 4)))
+  ) ->
+  -- |
+  -- ( Outgoing 'Bittide.Link'
+  -- , Outgoing @Vector@ of slave busses
+  -- )
+  ( Signal dom (DataLink 64)
+  , Vec 4 (Signal dom (WishboneS2M (Bytes 4)))
+  )
+gppeM (GppeConfig linkConfig peConfig, linkIn, splitAtI -> (nmuM2S0, nmuM2S1)) =
+  (linkOut, nmuS2M0 ++ nmuS2M1)
+ where
+  (suS2M, nmuS2M0) = linkToPe linkConfig linkIn sc suM2S nmuM2S0
+  (linkOut, guS2M, nmuS2M1) = peToLink linkConfig sc guM2S nmuM2S1
+  (_, nmuM2Ss) = toSignals (processingElementM peConfig) (pure $ JtagIn low low low, nmuS2Ms)
+  (suM2S, guM2S) = vecToTuple nmuM2Ss
+  nmuS2Ms = suS2M :> guS2M :> Nil
+  sc = sequenceCounter
+
 {-# NOINLINE managementUnit #-}
 
 {- | A special purpose 'processingElement' that manages a Bittide Node. It contains

bittide/src/Bittide/ScatterGather.hs

@@ -8,20 +8,28 @@
 
 module Bittide.ScatterGather (
   scatterUnitWb,
+  scatterUnitM,
   ScatterConfig (..),
   gatherUnitWb,
+  gatherUnitM,
   GatherConfig (..),
 ) where
 
 import Clash.Prelude
 
+
+import Protocols
+import Protocols.MemoryMap
 import Protocols.Wishbone
 
 import Bittide.Calendar
 import Bittide.DoubleBufferedRam
 import Bittide.Extra.Maybe
 import Bittide.SharedTypes
 
+import Data.Constraint
+import Data.Constraint.Nat.Extra
+
 {- | Existential type to explicitly differentiate between a configuration for
 the 'scatterUnitWb' and 'gatherUnitWb' at type level and hide the memory depth from
 higher level APIs.
@@ -188,6 +196,46 @@ addStalling endOfMetacycle (incomingBus@WishboneS2M{..}, wbAddr, writeOp0) =
     | otherwise = (incomingBus, writeOp0)
   memAddr = bitCoerce $ resize wbAddr
 
+scatterUnitM ::
+  forall dom addrWidthSu nBytesCal addrWidthCal.
+  ( HiddenClockResetEnable dom
+  , KnownNat addrWidthSu
+  , 2 <= addrWidthSu
+  , KnownNat nBytesCal
+  , 1 <= nBytesCal
+  , KnownNat addrWidthCal
+  , 2 <= addrWidthCal
+  ) =>
+  -- | Configuration for the 'calendar'.
+  ScatterConfig nBytesCal addrWidthCal ->
+  Circuit
+    ( MemoryMapped (Wishbone dom 'Standard addrWidthSu (Bytes 4))
+    , Wishbone dom 'Standard addrWidthCal (Bytes nBytesCal)
+    , CSignal dom (DataLink 64))
+    ()
+scatterUnitM config = Circuit go
+ where
+  go :: ((Signal dom (WishboneM2S addrWidthSu 4 (BitVector 32)),
+               Signal
+                 dom
+                 (WishboneM2S
+                    addrWidthCal
+                    (Div ((nBytesCal * 8) + 7) 8)
+                    (BitVector (nBytesCal * 8))),
+               Signal dom (Maybe (BitVector 64))),
+              ())
+             -> (((SimOnly MemoryMap, Signal dom (WishboneS2M (BitVector 32))),
+                  Signal dom (WishboneS2M (BitVector (nBytesCal * 8))),
+                  Signal dom ()),
+                 ())
+  go ((m2s, m2sCal, dataLink), ()) = (((SimOnly undefined, s2m), s2mCal, pure ()), ())
+   where
+    (s2m, s2mCal) = case cancelMulDiv @nBytesCal @8 of
+      Dict ->
+        scatterUnitWb config m2sCal dataLink m2s
+
+
+
 {-# NOINLINE scatterUnitWb #-}
 
 {- | Wishbone addressable 'scatterUnit', the wishbone port can read the data from this
@@ -231,6 +279,39 @@ scatterUnitWb (ScatterConfig calConfig) wbInCal linkIn wbInSu =
   selected = register (errorX "scatterUnitWb: Initial selection undefined") upperSelected
   scatteredData = mux selected upper lower
 
+
+gatherUnitM ::
+  forall dom addrWidthGu nBytesCal addrWidthCal.
+  ( HiddenClockResetEnable dom
+  , KnownNat addrWidthGu
+  , 2 <= addrWidthGu
+  , KnownNat nBytesCal
+  , 1 <= nBytesCal
+  , KnownNat addrWidthCal
+  , 2 <= addrWidthCal
+  ) =>
+  -- | Configuration for the 'calendar'.
+  GatherConfig nBytesCal addrWidthCal ->
+  Circuit
+    ( MemoryMapped (Wishbone dom 'Standard addrWidthGu (Bytes 4))
+    , Wishbone dom 'Standard addrWidthCal (Bytes nBytesCal))
+    (CSignal dom (DataLink 64))
+gatherUnitM config = Circuit go
+ where
+  go :: (( Signal dom (WishboneM2S addrWidthGu 4 (BitVector 32))
+         , Signal dom (WishboneM2S addrWidthCal (Div ((nBytesCal * 8) + 7) 8) (BitVector (nBytesCal * 8)))
+         )
+        , Signal dom ()
+        ) ->
+        (((SimOnly MemoryMap, Signal dom (WishboneS2M (BitVector 32)))
+         , Signal dom (WishboneS2M (BitVector (nBytesCal * 8))))
+        , Signal dom (Maybe (BitVector 64)))
+  go ((m2s, m2sCal), _) = (((SimOnly undefined, s2m), s2mCal), dataLink)
+   where
+    (dataLink, s2m, s2mCal) = case cancelMulDiv @nBytesCal @8 of
+      Dict ->
+        gatherUnitWb config m2sCal m2s
+
 {-# NOINLINE gatherUnitWb #-}
 
 {- | Wishbone addressable 'gatherUnit', the wishbone port can write data to this

clash-protocols-memmap/app/Example.hs

@@ -1,4 +1,4 @@
--- SPDX-FileCopyrightText: 2022-2024 Google LLC
+-- SPDX-FileCopyrightText: 2022 Google LLC
 --
 -- SPDX-License-Identifier: Apache-2.0
 {-# LANGUAGE CPP #-}

firmware-binaries/examples/hello/Cargo.toml

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2024 Google LLC
+# SPDX-FileCopyrightText: 2022 Google LLC
 #
 # SPDX-License-Identifier: CC0-1.0