Add pre-process step and a driver function to the test infrastructure

.github/synthesis/debug.json

@@ -0,0 +1,3 @@
+[
+  {"top": "vexRiscvTcpTest",               "stage": "test"}
+]

bittide-experiments/bittide-experiments.cabal

@@ -106,6 +106,7 @@ library
     text,
     typelits-witnesses,
     vector,
+    vivado-hs,
 
   exposed-modules:
     Bittide.Github.Artifacts
@@ -153,5 +154,6 @@ test-suite doctests
     base,
     bittide-experiments,
     doctest-parallel >=0.3.0.1 && <0.4,
+    word8,
 
   default-language: Haskell2010

bittide-experiments/src/Bittide/Hitl.hs

@@ -41,16 +41,19 @@ Tests are collected in @Bittide.Instances.Hitl.Tests@.
 module Bittide.Hitl (
   ClashTargetName,
   FpgaId,
+  DeviceInfo (..),
   HwTargetRef (..),
 
   -- * Test definition
   HitlTestGroup (..),
   HitlTestCase (..),
+  TestStepResult (..),
   MayHavePostProcData (..),
   Done,
   Success,
   hitlVio,
   hitlVioBool,
+  noPreProcess,
 
   -- * Test construction convenience functions
   paramForHwTargets,
@@ -62,7 +65,13 @@ where
 
 import Prelude
 
-import Clash.Prelude (BitPack (BitSize), KnownDomain, Vec (Nil, (:>)), natToInteger)
+import Clash.Prelude (
+  BitPack (BitSize),
+  BitVector,
+  KnownDomain,
+  Vec (Nil, (:>)),
+  natToInteger,
+ )
 
 import Clash.Cores.Xilinx.VIO (vioProbe)
 
@@ -76,6 +85,11 @@ import Numeric.Natural (Natural)
 import Clash.Prelude qualified as P
 import Data.Map.Strict qualified as Map
 
+import System.Exit (ExitCode)
+
+import Vivado (VivadoHandle)
+import Vivado.Tcl (HwTarget)
+
 {- | Fully qualified name to a function that is the target for Clash
 compilation. E.g. @Bittide.Foo.topEntity@.
 -}
@@ -89,12 +103,25 @@ For example, the ID of hardware target
 -}
 type FpgaId = String
 
+data DeviceInfo = DeviceInfo
+  { deviceId :: String
+  , dna :: BitVector 96
+  , serial :: String
+  , usbAdapterLocation :: String
+  }
+  deriving (Eq, Ord, Show)
+
 {- | A reference to an FPGA hardware target, either by index/relative position
 in the Bittide demo rig or by ID.
 -}
 data HwTargetRef
   = HwTargetByIndex Natural
-  | HwTargetById FpgaId
+  | HwTargetById FpgaId DeviceInfo
+  deriving (Eq, Ord, Show)
+
+data TestStepResult a
+  = TestStepSuccess a
+  | TestStepFailure String
   deriving (Eq, Ord, Show)
 
 {- | A definition of a test that should be performed with hardware in the loop.
@@ -174,11 +201,13 @@ data HitlTestGroup where
     , extraXdcFiles :: [String]
     , testCases :: [HitlTestCase HwTargetRef a b]
     -- ^ List of test cases
-    , mPostProc :: Maybe String
-    -- ^ Optional post processing step. If present, the name of the executable
-    -- in the @bittide-instances@ package.
+    , mDriverProc ::
+        Maybe (VivadoHandle -> String -> FilePath -> [(HwTarget, DeviceInfo)] -> IO ExitCode)
+    -- ^ Optional function driving the test after pre-processing.
+    , mPostProc :: Maybe (FilePath -> ExitCode -> IO (TestStepResult ()))
+    -- ^ Optional post processing step.
     , externalHdl :: [String]
-    -- ^ List of external HDL files to include in the project
+    -- ^ List of external HDL files to include in he project
     } ->
     HitlTestGroup
 
@@ -213,6 +242,11 @@ instance MayHavePostProcData a where
 instance MayHavePostProcData () where
   mGetPPD = Map.fromList . map ((,Nothing) . name)
 
+-- | Pre-process function that always succeeds and uses '()' as user-data.
+noPreProcess ::
+  VivadoHandle -> String -> FilePath -> HwTarget -> DeviceInfo -> IO (TestStepResult ())
+noPreProcess _ _ _ _ _ = pure (TestStepSuccess ())
+
 -- | Obtain a list of the hardware targets that are relevant for a given HITL test.
 hwTargetRefsFromHitlTestGroup :: HitlTestGroup -> [HwTargetRef]
 hwTargetRefsFromHitlTestGroup HitlTestGroup{testCases} =
@@ -240,8 +274,16 @@ to it and receives that constructur as test parameter.
 > testCases = testCasesFromEnum @ABC allHwTargets ()
 -}
 testCasesFromEnum ::
+  -- forall a b c.
   forall a b.
-  (Show a, Bounded a, Enum a, BitPack a, Show b, Typeable a, Typeable b) =>
+  ( Show a
+  , Bounded a
+  , Enum a
+  , BitPack a
+  , Show b
+  , Typeable a
+  , Typeable b
+  ) =>
   [HwTargetRef] ->
   b ->
   [HitlTestCase HwTargetRef a b]

bittide-experiments/src/Bittide/Plot.hs

@@ -41,7 +41,7 @@ import Graphics.Matplotlib (
 import Graphics.Matplotlib qualified as MP (plot)
 
 import Bittide.ClockControl (RelDataCount)
-import Bittide.ClockControl.Callisto (ReframingState (..))
+import Bittide.ClockControl.Callisto.Types (ReframingState (..))
 import Bittide.ClockControl.StabilityChecker qualified as SC (StabilityIndication (..))
 import Bittide.Topology
 

bittide-instances/bittide-instances.cabal

@@ -76,6 +76,7 @@ common common-options
 
   default-language: Haskell2010
   build-depends:
+    Glob,
     MissingH,
     aeson,
     async,
@@ -91,9 +92,11 @@ common common-options
     clash-prelude,
     clash-protocols,
     clash-vexriscv,
+    clock,
     constraints >=0.13.3 && <0.15,
     containers,
     cryptohash-sha256,
+    deepseq,
     directory,
     extra,
     filepath,
@@ -118,6 +121,8 @@ common common-options
     time,
     unix,
     vector,
+    vivado-hs,
+    word8,
 
 library
   import: common-options
@@ -127,22 +132,27 @@ library
     Bittide.Instances.Hacks
     Bittide.Instances.Hitl.BoardTest
     Bittide.Instances.Hitl.DnaOverSerial
+    Bittide.Instances.Hitl.Driver.DnaOverSerial
+    Bittide.Instances.Hitl.Driver.SwCcTopologies
+    Bittide.Instances.Hitl.Driver.VexRiscv
+    Bittide.Instances.Hitl.Driver.VexRiscvTcp
     Bittide.Instances.Hitl.Ethernet
     Bittide.Instances.Hitl.FincFdec
     Bittide.Instances.Hitl.IlaPlot
     Bittide.Instances.Hitl.LinkConfiguration
     Bittide.Instances.Hitl.Post.BoardTestExtended
     Bittide.Instances.Hitl.Post.PostProcess
-    Bittide.Instances.Hitl.Post.TcpServer
     Bittide.Instances.Hitl.Setup
     Bittide.Instances.Hitl.SwCcTopologies
     Bittide.Instances.Hitl.SyncInSyncOut
     Bittide.Instances.Hitl.TemperatureMonitor
     Bittide.Instances.Hitl.Tests
     Bittide.Instances.Hitl.Transceivers
+    Bittide.Instances.Hitl.Utils.Gdb
+    Bittide.Instances.Hitl.Utils.Program
+    Bittide.Instances.Hitl.Utils.Vivado
     Bittide.Instances.Hitl.VexRiscv
     Bittide.Instances.Pnr.Calendar
-    Bittide.Instances.Pnr.ClockControl
     Bittide.Instances.Pnr.Counter
     Bittide.Instances.Pnr.ElasticBuffer
     Bittide.Instances.Pnr.Ethernet
@@ -153,7 +163,6 @@ library
     Bittide.Instances.Pnr.Synchronizer
     Paths.Bittide.Instances
     Project.Handle
-    Project.Programs
 
   other-modules:
     Paths_bittide_instances
@@ -220,71 +229,3 @@ executable clash
     bittide-instances,
     clash-ghc,
     vivado-hs,
-
-executable post-board-test-extended
-  import: common-options
-  ghc-options:
-    -Wall
-    -Wcompat
-    -threaded
-
-  main-is: exe/post-board-test-extended/Main.hs
-  build-depends:
-    Glob,
-    bittide-instances,
-    filepath,
-
-executable post-vex-riscv-test
-  import: common-options
-  ghc-options:
-    -Wall
-    -Wcompat
-    -threaded
-
-  main-is: exe/post-vex-riscv-test/Main.hs
-  build-depends:
-    bittide-instances,
-    extra,
-    process,
-    tasty,
-    tasty-hunit,
-    tasty-th,
-    temporary,
-
-  other-modules: Paths_bittide_instances
-
-executable post-vex-riscv-tcp-test
-  import: common-options
-  ghc-options:
-    -Wall
-    -Wcompat
-    -threaded
-
-  main-is: exe/post-vex-riscv-tcp-test/Main.hs
-  build-depends:
-    bittide-instances,
-    extra,
-    process,
-    tasty,
-    tasty-hunit,
-    tasty-th,
-    temporary,
-
-  other-modules: Paths_bittide_instances
-
-executable post-dna-over-serial
-  import: common-options
-  ghc-options:
-    -Wall
-    -Wcompat
-    -threaded
-
-  main-is: exe/post-dna-over-serial/Main.hs
-  build-depends:
-    bittide-instances,
-    process,
-    tasty,
-    tasty-hunit,
-    tasty-th,
-
-  other-modules: Paths_bittide_instances

bittide-instances/data/constraints/jtag_pmod1-alt.xdc

@@ -0,0 +1,16 @@
+# SPDX-FileCopyrightText: 2024 Google LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# PMOD1_[0..7]
+# Note that there are no clock capable pins in this list
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AP16} [get_ports {JTAG_TCK}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AP15} [get_ports {JTAG_TDI}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM16} [get_ports {JTAG_RST}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM15} [get_ports {JTAG_TMS}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN18} [get_ports {JTAG_TDO}]
+
+# PMOD1 does not have a clock capable pin. To Vivado's credit, it refuses to
+# produce a bitstream if we try to use a non-clock capable pin as a clock. With
+# the following line, we tell Vivado to ignore this warning.
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTAG_TCK]