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Implement Verilog output stream PanamaCIRCTConverter
#3520
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PanamaCIRCTConverter
We notice width truncation was broken when we try to elaborate the T1 testbench, thanks @seldridge, pointed me the link saying parser is adding additional ops for padding. Since it is stricter, I will personally force T1 and rocket-chip to avoid width padding and trunction in connect, and fix them. But this is an issue we should try to fix in the future, here are some possible solutions:
Since we didn't release panama converter, and won't release it to normal user in a near future, when that day comes, we may already fix this issue. So it won't block the merging of this PR. For any project which tries to use this feature. please fix the this issue in your user code. |
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refer to: - openjdk/jdk#13079 - llvm-project/circt dadf87b742f547840f6866beb50bdf46a76d3fed
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Change in this PR doesn't affect the review flow, and possibly not be included in Chisel 6, so I mark this as internal
.
After this PR, the chisel-circt-binding project is able to emit Verilog by calling CIRCT C-API, thanks hard work by @SpriteOvO
The next milestone should possibly be pass plugin, e.g:
- inspect
Property
via Scala.
This feature is in a very early stage! please don't use in production flow for now!
* Implement Verilog output stream `PanamaCIRCTConverter` * Truncate or pad when connecting ports with different widths * Use `scala.math.BigInt.bitLength` instead of our own `bitLength` * Use correct module name for instances * Binder introduces Firtool options * fix binder for JDK21 and firtool 1.67.0 refer to: - openjdk/jdk#13079 - llvm-project/circt dadf87b742f547840f6866beb50bdf46a76d3fed * fix for review * reformat * bump GitHub CI to JDK 21 and mill 0.11.5 * remove 2.13.0 to 2.13.10 for JDK21 in build.sc ref to: scala/bug#12783 --------- Co-authored-by: Jiuyang Liu <[email protected]>
Based on llvm/circt#6094 and llvm/circt#6036.
We are trying to reimplement CIRCTfirtool
in Chisel, with it, we can select and manipulate passes to export to targets with the newCIRCTConverter
in #3466.This PR implements Verilog output stream PanamaCIRCTConverter
This PR is at a very early stage, opening the PR for discussion.
Contributor Checklist
docs/src
?Type of Improvement
Desired Merge Strategy
Release Notes
Reviewer Checklist (only modified by reviewer)
3.5.x
,3.6.x
, or5.x
depending on impact, API modification or big change:6.0
)?Enable auto-merge (squash)
, clean up the commit message, and label withPlease Merge
.Create a merge commit
.