Fix RoCCCSRIO bidir (#3518)

(cherry picked from commit b47fdf9) Co-authored-by: Jerry Zhao <[email protected]>
chipsalliance · Nov 1, 2023 · f11fb1a · f11fb1a
1 parent e377336
commit f11fb1a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
@@ -185,7 +185,7 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
     core.io.rocc.resp <> respArb.get.io.out
     core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _))
     core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _)
-    (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 := t._1 }
+    (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 }
   } else {
     // tie off
     core.io.rocc.cmd.ready := false.B