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Prevent bypasses from vector instructions | fix vsets #3670

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merged 2 commits into from
Aug 16, 2024
Merged

Prevent bypasses from vector instructions | fix vsets #3670

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49158aa
Prevent bypasses from vector instructions
jerryz123 Aug 15, 2024
72690b0
Fix bit indices for rd when computing AVL for vsets
jerryz123 Aug 16, 2024
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6 changes: 3 additions & 3 deletions src/main/scala/rocket/RocketCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -490,7 +490,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
!ex_reg_inst(31) -> ex_reg_inst(30,20))))
val ex_avl = Mux(ex_ctrl.rxs1,
Mux(ex_reg_inst(19,15) === 0.U,
Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax),
Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax),
ex_rs(0)
),
ex_reg_inst(19,15))
Expand Down Expand Up @@ -985,7 +985,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
sboard.set(wb_set_sboard && wb_wen, wb_waddr)

// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc
val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec
val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr)
val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr)
val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
Expand All @@ -994,7 +994,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
val mem_mem_cmd_bh =
if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass
else true.B
val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc
val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec
val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr)
val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem)
Expand Down
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