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VM disabled: support larger physical addresses #3682

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Sep 1, 2024
Merged

VM disabled: support larger physical addresses #3682

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2 changes: 1 addition & 1 deletion src/main/scala/rocket/CSR.scala
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Expand Up @@ -149,7 +149,7 @@ class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
case 32 => (1, 9)
case 64 => (4, 16)
}
require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen)
require(!usingVM || modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen)

val mode = UInt(modeBits.W)
val asid = UInt(maxASIdBits.W)
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2 changes: 1 addition & 1 deletion src/main/scala/rocket/PTW.scala
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Expand Up @@ -303,7 +303,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
val (pte, invalid_paddr, invalid_gpa) = {
val tmp = mem_resp_data.asTypeOf(new PTE())
val res = WireDefault(tmp)
res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0))
res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits.min(tmp.ppn.getWidth)-1, 0))
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
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2 changes: 1 addition & 1 deletion src/main/scala/rocket/TLB.scala
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Expand Up @@ -403,7 +403,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough

// share a single physical memory attribute checker (unshare if critical path)
val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
val refill_ppn = if (usingVM) io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) else 0.U
/** refill signal */
val do_refill = usingVM.B && io.ptw.resp.valid
/** sfence invalidate refill */
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6 changes: 5 additions & 1 deletion src/main/scala/tile/BaseTile.scala
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Expand Up @@ -83,7 +83,11 @@ trait HasNonDiplomaticTileParameters {
def vmIdBits: Int = p(VMIdBits)
lazy val maxPAddrBits: Int = {
require(xLen == 32 || xLen == 64, s"Only XLENs of 32 or 64 are supported, but got $xLen")
xLen match { case 32 => 34; case 64 => 56 }
((xLen, usingVM): @unchecked) match {
case (_, false) => xLen
case (32, true) => 34
case (64, true) => 56
}
}

def tileId: Int = tileParams.tileId
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