[rtl] complete stdlib Queue and add "almost" ports #823
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sequencer
reviewed
Nov 1, 2024
stdlib/src/Queue.scala
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| val io = Wire(new QueueIO(gen)) | ||
| if (entries == 1) { | ||
| val data = Reg(gen) |
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Suggested change
| val data = Reg(gen) | |
| val data = if(resetMem)RegInit(0.U.asTypeOf(gen))else(Reg(gen)) |
Signed-off-by: unlsycn <[email protected]>
sequencer
approved these changes
Nov 1, 2024
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