wirelength_analyzer to check PIP tile before assigning zero WL (Xilin…

…x#34) * wirelength_analyzer to check PIP tile before assigning zero WL Signed-off-by: Eddie Hung <[email protected]> * Be more strict with 'INT_' prefix Signed-off-by: Eddie Hung <[email protected]> * Add more tile names for in-context ispd16_example2 Signed-off-by: Eddie Hung <[email protected]> * Rename variable Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]>
eddieh-xlnx · Oct 31, 2023 · 718a308 · 718a308
1 parent 1cb95b9
commit 718a308
Showing 1 changed file with 16 additions and 9 deletions.
diff --git a/wirelength_analyzer/wa.py b/wirelength_analyzer/wa.py
@@ -18,6 +18,7 @@
 import warnings
 import itertools
 from xcvup_device_data import xcvupDeviceData
+import re
 
 class WirelengthAnalyzer:
     """
@@ -115,6 +116,7 @@ def __init__(self, netlist, verbosity=0):
         self.placements = {}
         for c in self.phys.placements:
             self.placements[(c.site, c.bel)] = c
+        self.tile_root_name_regex = re.compile(r'(.+)_X\d+Y\d+')
         self.add_all_nets_to_graph()
 
     def tstart(self):
@@ -249,18 +251,23 @@ def segment_to_wirelength(self, seg):
         if seg.which() == 'pip':
             wire1 = seg.pip.wire1
             tile  = seg.pip.tile
-
-            is_tile = self.tile_cache.get(tile)
-            if is_tile is None:
-                tile_name = self.phys.strList[tile]
-                is_tile = tile_name.startswith('INT')
-                self.tile_cache[tile] = is_tile
-
-            if is_tile:
+            sl = self.phys.strList
+
+            is_int_tile = self.tile_cache.get(tile)
+            if is_int_tile is None:
+                tile_name = sl[tile]
+                is_int_tile = tile_name.startswith('INT_')
+                self.tile_cache[tile] = is_int_tile
+                if not is_int_tile and self.tile_root_name_regex.match(tile_name).group(1) not in \
+                    ('CLEL_R', 'CLEM', 'CLEM_R', 'BRAM', 'DSP',
+                     'XIPHY_BYTE_L', 'HPIO_L', 'CMT_L'):
+                    raise ValueError("Unrecognized tile on PIP: " + tile_name + ',' +  sl[seg.pip.wire0] + ',' + sl[wire1])
+
+            if is_int_tile:
                 wl = self.pip_cache.get(wire1)
                 if wl is not None:
                     return wl
-                wire1_name = self.phys.strList[wire1]
+                wire1_name = sl[wire1]
                 for p in self.pips:
                     if p[0].fullmatch(wire1_name):
                         self.pip_cache[wire1] = p[1]