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pyverilog: fix preprocessor output conflicts
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ekiwi committed Jan 16, 2024
1 parent 1c52a02 commit 08d22b3
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Showing 2 changed files with 23 additions and 11 deletions.
8 changes: 2 additions & 6 deletions pyverilog/vparser/parser.py
Original file line number Diff line number Diff line change
Expand Up @@ -2643,9 +2643,8 @@ class ParseError(Exception):

class VerilogCodeParser(object):

def __init__(self, filelist, preprocess_output='preprocess.output',
def __init__(self, filelist, preprocess_output=None,
preprocess_include=None, preprocess_define=None):
self.preprocess_output = preprocess_output
self.directives = ()
self.preprocessor = VerilogPreprocessor(filelist, preprocess_output,
preprocess_include,
Expand All @@ -2654,10 +2653,7 @@ def __init__(self, filelist, preprocess_output='preprocess.output',

def preprocess(self):
self.preprocessor.preprocess()
with open(self.preprocess_output) as f:
text = f.read()
os.remove(self.preprocess_output)
return text
return self.preprocessor.read_output(remove=True)

def parse(self, preprocess_output='preprocess.output', debug=0):
text = self.preprocess()
Expand Down
26 changes: 21 additions & 5 deletions pyverilog/vparser/preprocessor.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@


class VerilogPreprocessor(object):
def __init__(self, filelist, outputfile='pp.out', include=None, define=None):
def __init__(self, filelist, outputfile=None, include=None, define=None):

if not isinstance(filelist, (tuple, list)):
filelist = list(filelist)
Expand Down Expand Up @@ -79,25 +79,41 @@ def __init__(self, filelist, outputfile='pp.out', include=None, define=None):

self.iv.append('-E')
self.iv.append('-o')
self.iv.append(outputfile)

# create a temporary file if necessary
if outputfile is None:
ff = tempfile.NamedTemporaryFile('w', delete=False)
ff.close()
self.outputfile = ff.name
else:
self.outputfile = outputfile

def preprocess(self):
cmd = self.iv + list(self.filelist)
cmd = self.iv + [self.outputfile] + list(self.filelist)
subprocess.call(cmd)

# Removing the temporary files that were created
for temp_file_path in self.temp_files_paths:
os.remove(temp_file_path)

def read_output(self, remove: bool) -> str:
assert(os.path.isfile(self.outputfile), f"{self.outputfile} does not exist or is not a file!")
with open(self.outputfile) as f:
text = f.read()
if remove:
os.remove(self.outputfile)
return text


def preprocess(
filelist,
output='preprocess.output',
output=None,
include=None,
define=None
):
pre = VerilogPreprocessor(filelist, output, include, define)
pre.preprocess()
text = open(output).read()
with open(output) as f:
text = f.read()
os.remove(output)
return text

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