preprocess: assign 0 by default

ekiwi · Jan 6, 2024 · 1e8b6b9 · 1e8b6b9
1 parent f0725e4
commit 1e8b6b9
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Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/rtlrepair/preprocess.py b/rtlrepair/preprocess.py
@@ -148,13 +148,15 @@ def filter_warnings(warnings: list) -> list:
 
 _latch_re = re.compile(r"Latch inferred for signal '([^']+)'")
 
+# TODO: maybe change back to 0
+_default_value = "'d0"
 
 def assign_latch_signal(latch_warning: LintWarning):
     m = _latch_re.search(latch_warning.msg)
     assert m is not None, latch_warning.msg
     signal_parts = m.group(1).split(".")
     ident = vast.Identifier(signal_parts[-1].strip())
-    return vast.BlockingSubstitution(vast.Lvalue(ident), vast.Rvalue(vast.IntConst("'d1")))
+    return vast.BlockingSubstitution(vast.Lvalue(ident), vast.Rvalue(vast.IntConst(_default_value)))
 
 
 class LintFixer(AstVisitor):

diff --git a/test.py b/test.py
@@ -341,7 +341,7 @@ def test_sdram_kgoliya2(self):
         # CirFix: timeout
         changes = self.synth_success(sd_dir / "no_tri_state.toml", "kgoliya_buggy2", solver=self.solver, init=self.init,
                                      incremental=self.incremental, timeout=self.timeout)
-        self.assertEqual(1, changes)  # repaired by pre-processing + assign const!
+        self.assertEqual(2, changes)  # repaired by pre-processing alone
 
     def test_i2c_master_kgoliya1(self):
         # CirFix: incorrect repair