bench: add axi stream projec toml and to btor

ekiwi · Jan 6, 2024 · 436e1d7 · 436e1d7
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diff --git a/benchmarks/fpga-debugging/axi-stream-s2/project.toml b/benchmarks/fpga-debugging/axi-stream-s2/project.toml
@@ -0,0 +1,14 @@
+[project]
+directory = "."
+sources = ["xlnxstream_2018_3.v"]
+toplevel = "xlnxstream_2018_3"
+
+[[bugs]]
+name = "s2"
+original = "xlnxstream_2018_3.v"
+buggy = "xlnxstream_2018_3_bug_s2.v"
+
+
+[[testbenches]]
+name = "csv"
+table = "tb.csv"
diff --git a/benchmarks/fpga-debugging/axi-stream-s2/to_btor2.ys b/benchmarks/fpga-debugging/axi-stream-s2/to_btor2.ys
@@ -0,0 +1,17 @@
+# read_sources
+read_verilog xlnxstream_2018_3.v
+
+hierarchy -top xlnxstream_2018_3
+
+# minimal btor
+proc -noopt
+
+# extra
+opt
+
+async2sync
+flatten
+dffunmap
+
+
+write_btor -x xlnxstream_2018_3_axi_stream.btor