fix width inference

rtlrepair/types.py

@@ -153,7 +153,7 @@ def eval(self, node: vast.Node) -> int:
         return value
 
     def determine_var_width(self, node):
-        assert isinstance(node, vast.Variable) or isinstance(node, vast.Parameter)
+        assert isinstance(node, vast.Variable) or isinstance(node, vast.Parameter) or isinstance(node, vast.Input) or isinstance(node, vast.Output)
         explicit_width = self.eval(node.width)
         if explicit_width is not None:  # if there is an explicit width annotated, take that
             self.vars[node.name] = explicit_width
@@ -163,7 +163,7 @@ def determine_var_width(self, node):
             self.vars[node.name] = 1
 
     def generic_visit(self, node):
-        if isinstance(node, vast.Variable):
+        if isinstance(node, vast.Variable) or isinstance(node, vast.Input)  or isinstance(node, vast.Output):
             self.determine_var_width(node)
         elif isinstance(node, vast.Parameter):
             self.determine_var_width(node)
@@ -180,6 +180,10 @@ def generic_visit(self, node):
             self.expr_width(node.cond, 1)
             self.visit(node.true_statement)
             self.visit(node.false_statement)
+        elif isinstance(node, vast.CaseStatement):
+            self.expr_width(node.comp, 1)
+            for c in node.caselist:
+                self.visit(c)
         elif isinstance(node, vast.Value) or isinstance(node, vast.Operator):
             self.expr_width(node, None)
         else:

test.py

@@ -49,6 +49,7 @@ def run_synth(project_path: Path, bug: str, testbench: str = None, solver='z3',
         "--solver", solver,
         "--working-dir", str(out_dir.resolve()),
         "--init", init,
+        "--verbose-synthesizer",
     ]
     if bug: # bug is optional to allow for sanity-check "repairs" of the original design
         args += ["--bug", bug]
@@ -177,8 +178,9 @@ def test_fsm_full_ssscrazy2(self):
 
     def test_fsm_full_wadden1(self):
         # CirFix: timed out
-        self.synth_cannot_repair(fsm_dir, "wadden_buggy1", solver=self.solver, init=self.init,
+        self.synth_success(fsm_dir, "wadden_buggy1", solver=self.solver, init=self.init,
                                  incremental=self.incremental, timeout=self.timeout)
+        # repaired by extended assign const
 
     def test_fsm_full_wadden2(self):
         # CirFix: incorrect repair
@@ -608,6 +610,14 @@ def test_i2c_bit_widths(self):
         expected = {None: 1, 1: 69, 2: 15, 3: 11, 4: 5, 14: 4, 16: 6, 18: 19, 32: 2}
         self.assertEqual(expected, hist)
 
+    def test_mux_widths(self):
+        from rtlrepair import parse_verilog
+        from rtlrepair.types import infer_widths
+        ast = parse_verilog(mux_dir / "mux_4_1.v")
+        widths = infer_widths(ast)
+        hist = _make_histogram(widths)
+        expected = {None: 1, 2: 5, 4: 5}
+        self.assertEqual(expected, hist)
 
 class TestExposeBranches(unittest.TestCase):
     """ unittests for code in rtlrepair/expose_branches.py """