bench: c4 CSV TB

ekiwi · Jan 5, 2024 · abeda8b · abeda8b
1 parent 6f11459
commit abeda8b
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Showing 5 changed files with 35 additions and 3 deletions.
diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/.gitignore b/benchmarks/fpga-debugging/axis-async-fifo-c4/.gitignore
@@ -0,0 +1 @@
+output.txt
diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/axis_async_fifo.v b/benchmarks/fpga-debugging/axis-async-fifo-c4/axis_async_fifo.v
@@ -64,7 +64,7 @@ module axis_async_fifo #
 reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] wr_ptr_next;
 reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}
+reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr_next;
 reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
 

diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/axis_async_fifo_bug_c4.v b/benchmarks/fpga-debugging/axis-async-fifo-c4/axis_async_fifo_bug_c4.v
@@ -64,7 +64,7 @@ module axis_async_fifo #
 reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] wr_ptr_next;
 reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}
+reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr_next;
 reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
 
@@ -102,7 +102,6 @@ wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
 
 assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg;
 
-// FIX: assign input_axis_tready = ~full  & ~input_rst_sync3;
 assign input_axis_tready = ~full;
 assign output_axis_tvalid = output_axis_tvalid_reg;
 

diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/tb.csv b/benchmarks/fpga-debugging/axis-async-fifo-c4/tb.csv
@@ -0,0 +1,11 @@
+async_rst, input_axis_tdata, input_axis_tvalid, input_axis_tready, input_axis_tlast, input_axis_tuser, output_axis_tdata, output_axis_tvalid, output_axis_tready, output_axis_tlast, output_axis_tuser
+1,  0,0,0,0,0,  0,0,0,0,0
+0,  1,0,0,0,0,  0,0,1,0,0
+0,  1,1,1,1,0,  0,0,1,0,0
+0,  2,1,x,1,0,  0,0,1,0,0
+0,  2,1,0,1,0,  0,0,1,0,0
+0,  2,1,1,1,0,  0,0,1,0,0
+0,  3,1,1,1,0,  0,0,1,0,0
+0,  4,1,1,1,0,  0,0,1,0,0
+0,  5,1,1,1,0,  0,0,1,0,0
+0,  6,1,1,1,0,  1,1,1,1,0
diff --git a/benchmarks/fpga-debugging/axis-async-fifo-c4/tb.v b/benchmarks/fpga-debugging/axis-async-fifo-c4/tb.v
@@ -57,6 +57,18 @@ wire output_axis_tvalid;
 wire output_axis_tlast;
 wire output_axis_tuser;
 
+integer f;
+// dump I/O
+initial begin
+  f = $fopen("output.txt");
+  $fwrite(f, "async_rst, input_axis_tdata, input_axis_tvalid, input_axis_tready, input_axis_tlast, input_axis_tuser, output_axis_tdata, output_axis_tvalid, output_axis_tready, output_axis_tlast, output_axis_tuser\n");
+  forever begin
+    @(posedge clk);
+    $fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n",async_rst, input_axis_tdata, input_axis_tvalid, input_axis_tready, input_axis_tlast, input_axis_tuser, output_axis_tdata, output_axis_tvalid, output_axis_tready, output_axis_tlast, output_axis_tuser);
+  end
+end
+
+
 initial begin
 
     async_rst = 1'b1;
@@ -126,4 +138,13 @@ UUT (
     .output_axis_tuser(output_axis_tuser)
 );
 
+
+`ifdef DUMP_TRACE // used for our OSDD calculations
+initial begin
+  $dumpfile("dump.vcd");
+  $dumpvars(0, UUT);
+end
+`endif // DUMP_TRACE
+
+
 endmodule