Merge pull request #2354 from antmicro/eos-upstream-common

EOS-S3 update [1/4]: update common cmake and utils

.github/scripts/install.sh

@@ -17,7 +17,7 @@ echo "----------------------------------------"
 
 heading "Set environment variables for F4PGA CLI utils"
 {
-  export F4PGA_FAM=xc7
+  export FPGA_FAM=xc7
   export F4PGA_INSTALL_DIR="placeholder"
   export F4PGA_ENV_BIN="$(cd $(dirname "$0"); pwd)/../../env/conda/envs/symbiflow_arch_def_base/bin"
   # TODO: We should place the content in subdir F4PGA_FAM, to use the default in f4pga instead of overriding F4PGA_ENV_SHARE here.

.github/scripts/ql.sh

@@ -1,9 +1,13 @@
 #!/usr/bin/env bash
 
+set -e
+
 INSTALL_DIR="$(pwd)/install"
 
 export CMAKE_FLAGS="-GNinja -DINSTALL_FAMILIES=qlf_k4n8,pp3 -DCMAKE_INSTALL_PREFIX=${INSTALL_DIR}"
 
+export FPGA_FAM=eos-s3
+export F4PGA_INSTALL_DIR="placeholder"
 source $(dirname "$0")/setup-and-activate.sh
 
 pushd build
@@ -15,11 +19,13 @@ heading "Running installed toolchain tests"
 (
 	pushd build
 	export CTEST_OUTPUT_ON_FAILURE=1
+	export F4PGA_ENV_SHARE=${INSTALL_DIR}/share/symbiflow
+	export F4PGA_ENV_BIN=${INSTALL_DIR}/bin/
 	heading "Testing installed toolchain on qlf_k4n8"
-	ctest -j${MAX_CORES} -R "quicklogic_toolchain_test_.*_qlf_k4n8" -VV || BUILD_RESULT=$?
+	ctest -j${MAX_CORES} -R "quicklogic_toolchain_test_.*_qlf_k4n8" -VV
 	echo "----------------------------------------"
 	heading "Testing installed toolchain on ql_eos_s3"
-	ctest -j${MAX_CORES} -R "quicklogic_toolchain_test_.*_ql-eos-s3" -VV || BUILD_RESULT=$?
+	ctest -j${MAX_CORES} -R "quicklogic_toolchain_test_.*_ql-eos-s3" -VV
 	echo "----------------------------------------"
 	popd
 )

common/cmake/devices.cmake

@@ -57,7 +57,6 @@ function(DEFINE_ARCH)
   #    BIT_TIME_CMD <command to run BIT_TIME>
   #    [RR_GRAPH_EXT <ext>]
   #    [NO_INSTALL]
-  #    [FIXUP_POST_SYNTHESIS_EXTRA_ARGS <extra args>]
   #   )
   # ~~~
   #
@@ -161,9 +160,6 @@ function(DEFINE_ARCH)
   # * OUT_BITSTREAM - Input path to bitstream.
   # * OUT_BIT_VERILOG - Output path to verilog version of bitstream.
   #
-  # FIXUP_POST_SYNTHESIS_EXTRA_ARGS allows to provide extra arguments for
-  # the utils/vpr_fixup_post_synth.py script.
-  #
   set(options
     NO_PLACE_CONSTR
     NO_PINS
@@ -213,7 +209,6 @@ function(DEFINE_ARCH)
     BIT_TIME_CMD
     RR_GRAPH_EXT
     ROUTE_CHAN_WIDTH
-    FIXUP_POST_SYNTHESIS_EXTRA_ARGS
   )
 
   set(
@@ -265,7 +260,6 @@ function(DEFINE_ARCH)
     NET_PATCH_TOOL_CMD
     BIT_TO_FASM
     BIT_TO_FASM_CMD
-    FIXUP_POST_SYNTHESIS_EXTRA_ARGS
     )
 
   set(PLACE_ARGS
@@ -1332,9 +1326,11 @@ function(ADD_FPGA_TARGET)
   #   [INPUT_XDC_FILES <input_xdc_files>]
   #   [INPUT_SDC_FILE <input_sdc_file>]
   #   [EXPLICIT_ADD_FILE_TARGET]
+  #   [AUTO_ADD_FILE_TARGET]
   #   [EMIT_CHECK_TESTS EQUIV_CHECK_SCRIPT <yosys to script verify two bitstreams gold and gate>]
   #   [NO_SYNTHESIS]
   #   [ASSERT_BLOCK_TYPES_ARE_USED <usage_spec>]
+  #   [ASSERT_TIMING <timing_spec>]
   #   [DEFINES <definitions>]
   #   [BIT_TO_V_EXTRA_ARGS]
   #   [NET_PATCH_EXTRA_ARGS]
@@ -1344,8 +1340,15 @@ function(ADD_FPGA_TARGET)
   #
   # ADD_FPGA_TARGET defines a FPGA build targetting a specific board.  By
   # default input files (SOURCES, TESTBENCH_SOURCES, INPUT_IO_FILE) will be
-  # implicitly passed to ADD_FILE_TARGET.  If EXPLICIT_ADD_FILE_TARGET is
+  # implicitly passed to ADD_FILE_TARGET. If EXPLICIT_ADD_FILE_TARGET is
   # supplied, this behavior is supressed.
+  # When AUTO_ADD_FILE_TARGETS is specified file targets will be created only if
+  # they do not exist already. AUTO_ADD_FILE_TARGETS is useful when multiple
+  # test designs share the same source files and there is no immediate possibility
+  # for putting CMakeLists.txt files along with them to define targets for
+  # EXPLICIT_ADD_FILE_TARGET. This is used for example in QuickLogic tests,
+  # there is a separate submodule with test designs that are used by
+  # multiple architectures (pp3, qlf_k4n8).
   #
   # TOP is the name of the top-level module in the design.  If no supplied,
   # TOP is set to "top".
@@ -1368,6 +1371,12 @@ function(ADD_FPGA_TARGET)
   # 	ASSERT_BLOCK_TYPES_ARE_USED	PB-CLOCK=1,PB-GMUX=1,PB-BIDIR=4
   # supported operators: =, <, <=, >, >=
   #
+  # ASSERT_TIMING enables tests that verify the timings of routed design
+  # against <timing_spec> which is a comma-separated list of
+  # relational expressions regarding design timing parameters, e.g:
+  # 	ASSERT_TIMING	fmax>=20.5
+  # supported operators: =, <, <=, >, >=
+  #
   # DEFINES is a list of environment variables to be defined during Yosys
   # invocation.
   #
@@ -1400,8 +1409,8 @@ function(ADD_FPGA_TARGET)
   # * ${TOP}.route - Place and routed design (http://docs.verilogtorouting.org/en/latest/vpr/file_formats/#routing-file-format-route)
   # * ${TOP}.${BITSTREAM_EXTENSION} - Bitstream for target.
   #
-  set(options EXPLICIT_ADD_FILE_TARGET EMIT_CHECK_TESTS NO_SYNTHESIS ROUTE_ONLY INSTALL_CIRCUIT)
-  set(oneValueArgs NAME TOP BOARD INPUT_IO_FILE EQUIV_CHECK_SCRIPT AUTOSIM_CYCLES ASSERT_BLOCK_TYPES_ARE_USED INPUT_SDC_FILE)
+  set(options EXPLICIT_ADD_FILE_TARGET AUTO_ADD_FILE_TARGET EMIT_CHECK_TESTS NO_SYNTHESIS ROUTE_ONLY INSTALL_CIRCUIT)
+  set(oneValueArgs NAME TOP BOARD INPUT_IO_FILE EQUIV_CHECK_SCRIPT AUTOSIM_CYCLES ASSERT_BLOCK_TYPES_ARE_USED ASSERT_TIMING INPUT_SDC_FILE)
   set(multiValueArgs SOURCES TESTBENCH_SOURCES DEFINES BIT_TO_V_EXTRA_ARGS INPUT_XDC_FILES NET_PATCH_EXTRA_ARGS)
   cmake_parse_arguments(
     ADD_FPGA_TARGET
@@ -1475,25 +1484,46 @@ function(ADD_FPGA_TARGET)
   if(NOT ${ADD_FPGA_TARGET_EXPLICIT_ADD_FILE_TARGET})
     if(NOT ${ADD_FPGA_TARGET_NO_SYNTHESIS})
       foreach(SRC ${ADD_FPGA_TARGET_SOURCES})
-        add_file_target(FILE ${SRC} SCANNER_TYPE verilog)
+        get_file_target(FILE_TARGET ${SRC})
+        if(NOT ${ADD_FPGA_TARGET_AUTO_ADD_FILE_TARGET} OR NOT TARGET ${FILE_TARGET})
+          add_file_target(FILE ${SRC} SCANNER_TYPE verilog)
+        endif()
       endforeach()
     else()
       foreach(SRC ${ADD_FPGA_TARGET_SOURCES})
-        add_file_target(FILE ${SRC})
+        get_file_target(FILE_TARGET ${SRC})
+        if(NOT ${ADD_FPGA_TARGET_AUTO_ADD_FILE_TARGET} OR NOT TARGET ${FILE_TARGET})
+          add_file_target(FILE ${SRC})
+        endif()
       endforeach()
     endif()
+
     foreach(SRC ${ADD_FPGA_TARGET_TESTBENCH_SOURCES})
-      add_file_target(FILE ${SRC} SCANNER_TYPE verilog)
+      get_file_target(FILE_TARGET ${SRC})
+      if(NOT ${ADD_FPGA_TARGET_AUTO_ADD_FILE_TARGET} OR NOT TARGET ${FILE_TARGET})
+        add_file_target(FILE ${SRC} SCANNER_TYPE verilog)
+      endif()
     endforeach()
 
     if(NOT "${ADD_FPGA_TARGET_INPUT_IO_FILE}" STREQUAL "")
-      add_file_target(FILE ${ADD_FPGA_TARGET_INPUT_IO_FILE})
+      get_file_target(FILE_TARGET ${ADD_FPGA_TARGET_INPUT_IO_FILE})
+      if(NOT ${ADD_FPGA_TARGET_AUTO_ADD_FILE_TARGET} OR NOT TARGET ${FILE_TARGET})
+        add_file_target(FILE ${ADD_FPGA_TARGET_INPUT_IO_FILE})
+      endif()
     endif()
+
     foreach(XDC ${ADD_FPGA_TARGET_INPUT_XDC_FILES})
-      add_file_target(FILE ${XDC})
+      get_file_target(FILE_TARGET ${XDC})
+      if(NOT ${ADD_FPGA_TARGET_AUTO_ADD_FILE_TARGET} OR NOT TARGET ${FILE_TARGET})
+        add_file_target(FILE ${XDC})
+      endif()
     endforeach()
+
     if(NOT "${ADD_FPGA_TARGET_INPUT_SDC_FILE}" STREQUAL "")
-      add_file_target(FILE ${ADD_FPGA_TARGET_INPUT_SDC_FILE})
+      get_file_target(FILE_TARGET ${SDC})
+      if(NOT ${ADD_FPGA_TARGET_AUTO_ADD_FILE_TARGET} OR NOT TARGET ${FILE_TARGET})
+        add_file_target(FILE ${ADD_FPGA_TARGET_INPUT_SDC_FILE})
+      endif()
     endif()
   endif()
 
@@ -1617,6 +1647,8 @@ function(ADD_FPGA_TARGET)
           ${QUIET_CMD} ${YOSYS} -r ${TOP} -p "${COMPLETE_YOSYS_SYNTH_SCRIPT}" -l ${OUT_JSON_SYNTH}.log ${SOURCE_FILES}
       COMMAND
         ${CMAKE_COMMAND} -E touch ${OUT_FASM_EXTRA}
+      COMMAND
+        ${CMAKE_COMMAND} -E touch ${OUT_SDC}
       WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
       VERBATIM
     )
@@ -1703,7 +1735,6 @@ function(ADD_FPGA_TARGET)
       NOT "${SDC_PATCH_TOOL}" STREQUAL "" AND
       NOT "${SDC_FILE}" STREQUAL "" AND
       NOT "${INPUT_IO_FILE}" STREQUAL "")
-    set(SDC_DEPS "")
 
     set(IN_SDC ${SDC_FILE})
 
@@ -2145,13 +2176,20 @@ function(ADD_FPGA_TARGET)
 
   # Generate routing.
   # -------------------------------------------------------------------------
+  set(ROUTE_LOG ${OUT_LOCAL}/route.log)
+
+  if(NOT "${ADD_FPGA_TARGET_ASSERT_TIMING}" STREQUAL "")
+      set(TIMING_SUMMARY ${OUT_LOCAL}/timing_summary.json)
+      list(APPEND VPR_ARGS --write_timing_summary ${TIMING_SUMMARY})
+  endif()
+
   add_custom_command(
-    OUTPUT ${OUT_ROUTE}
+    OUTPUT ${OUT_ROUTE} ${ROUTE_LOG} ${TIMING_SUMMARY}
     DEPENDS ${OUT_NET} ${OUT_PLACE} ${VPR_DEPS}
     COMMAND ${VPR_CMD} ${OUT_EBLIF} ${VPR_ARGS} --route
     COMMAND
       ${CMAKE_COMMAND} -E copy ${OUT_LOCAL}/vpr_stdout.log
-        ${OUT_LOCAL}/route.log
+      ${ROUTE_LOG}
     WORKING_DIRECTORY ${OUT_LOCAL}
   )
   add_custom_target(${NAME}_route DEPENDS ${OUT_ROUTE})
@@ -2165,11 +2203,22 @@ function(ADD_FPGA_TARGET)
     COMMAND ${VPR_CMD} ${OUT_EBLIF} ${VPR_ARGS} --echo_file on --route
     COMMAND
       ${CMAKE_COMMAND} -E copy ${OUT_LOCAL}/echo/vpr_stdout.log
-        ${OUT_LOCAL}/echo/route.log
+      ${OUT_LOCAL}/echo/route.log
     WORKING_DIRECTORY ${OUT_LOCAL}/echo
   )
   add_custom_target(${NAME}_route_echo DEPENDS ${ECHO_ATOM_NETLIST_ORIG})
 
+  if(NOT "${ADD_FPGA_TARGET_ASSERT_TIMING}" STREQUAL "")
+      set(TIMING_UTIL ${symbiflow-arch-defs_SOURCE_DIR}/utils/report_timing.py)
+      add_custom_target(
+          ${NAME}_assert_timing
+          COMMAND ${PYTHON3} ${TIMING_UTIL}
+            --assert \"${ADD_FPGA_TARGET_ASSERT_TIMING}\"
+            ${TIMING_SUMMARY}
+          DEPENDS ${PYTHON3} ${TIMING_UTIL} ${TIMING_SUMMARY}
+          )
+  endif()
+
   if(${ADD_FPGA_TARGET_ROUTE_ONLY})
     return()
   endif()
@@ -2246,34 +2295,17 @@ function(ADD_FPGA_TARGET)
 
   # Generate analysis.
   #-------------------------------------------------------------------------
-  set(FIXUP_POST_SYNTHESIS ${symbiflow-arch-defs_SOURCE_DIR}/utils/vpr_fixup_post_synth.py)
-
-  get_target_property(FIXUP_POST_SYNTHESIS_EXTRA_ARGS ${ARCH} FIXUP_POST_SYNTHESIS_EXTRA_ARGS)
-  if (NOT "${FIXUP_POST_SYNTHESIS_EXTRA_ARGS}" MATCHES ".*NOTFOUND" AND NOT "${FIXUP_POST_SYNTHESIS_EXTRA_ARGS}" STREQUAL "")
-    string(CONFIGURE ${FIXUP_POST_SYNTHESIS_EXTRA_ARGS} FIXUP_POST_SYNTHESIS_EXTRA_ARGS_FOR_TARGET)
-    separate_arguments(
-      FIXUP_POST_SYNTHESIS_EXTRA_ARGS_FOR_TARGET_LIST UNIX_COMMAND ${FIXUP_POST_SYNTHESIS_EXTRA_ARGS_FOR_TARGET}
-    )
-  else()
-    set(FIXUP_POST_SYNTHESIS_EXTRA_ARGS_FOR_TARGET_LIST)
-  endif()
 
   set(OUT_ANALYSIS ${OUT_LOCAL}/analysis.log)
-  set(OUT_POST_SYNTHESIS_V ${OUT_LOCAL}/${TOP}_post_synthesis.v)
+  set(OUT_POST_SYNTHESIS_V ${OUT_LOCAL}/${TOP}_merged_post_implementation.v)
   set(OUT_POST_SYNTHESIS_BLIF ${OUT_LOCAL}/${TOP}_post_synthesis.blif)
   set(OUT_POST_SYNTHESIS_SDF ${OUT_LOCAL}/${TOP}_post_synthesis.sdf)
   add_custom_command(
-    OUTPUT ${OUT_ANALYSIS} ${OUT_POST_SYNTHESIS_V} ${OUT_POST_SYNTHESIS_BLIF} ${OUT_POST_SYNTHESIS_SDF}
-    DEPENDS ${OUT_ROUTE} ${VPR_DEPS} ${PYTHON3} ${FIXUP_POST_SYNTHESIS}
-    COMMAND ${VPR_CMD} ${OUT_EBLIF} ${VPR_ARGS} --analysis --gen_post_synthesis_netlist on
+    OUTPUT ${OUT_ANALYSIS}
+    DEPENDS ${OUT_ROUTE} ${VPR_DEPS} ${PYTHON3}
+    COMMAND ${VPR_CMD} ${OUT_EBLIF} ${VPR_ARGS} --analysis --gen_post_synthesis_netlist on --gen_post_implementation_merged_netlist on --post_synth_netlist_unconn_inputs nets --post_synth_netlist_unconn_outputs nets
     COMMAND ${CMAKE_COMMAND} -E copy ${OUT_LOCAL}/vpr_stdout.log
         ${OUT_LOCAL}/analysis.log
-    COMMAND ${PYTHON3} ${FIXUP_POST_SYNTHESIS}
-        --vlog-in ${OUT_POST_SYNTHESIS_V}
-        --vlog-out ${OUT_POST_SYNTHESIS_V}
-        --sdf-in ${OUT_POST_SYNTHESIS_SDF}
-        --sdf-out ${OUT_POST_SYNTHESIS_SDF}
-        ${FIXUP_POST_SYNTHESIS_EXTRA_ARGS_FOR_TARGET_LIST}
     WORKING_DIRECTORY ${OUT_LOCAL}
     )
   add_custom_target(${NAME}_analysis DEPENDS ${OUT_ANALYSIS})

conda_lock.yml

@@ -81,7 +81,7 @@ dependencies:
   - symbiflow-yosys-plugins=1.0.0_7_832_ga2a80a1=20220317_162926
   - tbb=2020.3=hfd86e86_0
   - tk=8.6.11=h1ccaba5_0
-  - vtr-optimized=8.0.0_5310_g08ec56b5d=20220317_162926
+  - vtr-optimized=8.0.0_5338_g829c06d8f=20220409_131122
   - wheel=0.37.1=pyhd3eb1b0_0
   - xz=5.2.5=h7b6447c_0
   - yosys=0.15_51_g6318db615=20220317_162926_py37

quicklogic/common/cmake/quicklogic_install.cmake

@@ -88,10 +88,6 @@ function(DEFINE_QL_TOOLCHAIN_TARGET)
           DESTINATION bin/python/lib
           PERMISSIONS WORLD_READ OWNER_WRITE OWNER_READ GROUP_READ)
 
-  install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/utils/vpr_fixup_post_synth.py
-          DESTINATION bin/python
-          PERMISSIONS WORLD_READ OWNER_WRITE OWNER_READ GROUP_READ)
-
   install(FILES ${symbiflow-arch-defs_SOURCE_DIR}/quicklogic/common/utils/process_sdc_constraints.py
           DESTINATION bin/python
           PERMISSIONS WORLD_EXECUTE WORLD_READ OWNER_EXECUTE OWNER_WRITE OWNER_READ GROUP_EXECUTE GROUP_READ)

quicklogic/qlf_k4n8/CMakeLists.txt

@@ -21,9 +21,7 @@ set(VPR_ARCH_ARGS "\
     --place_delay_model delta_override \
     --router_lookahead extended_map \
     --allow_dangling_combinational_nodes on \
-    --absorb_buffer_luts off \
-    --post_synth_netlist_unconn_inputs nets \
-    --post_synth_netlist_unconn_outputs nets "
+    --absorb_buffer_luts off "
 )
 
 # Define the architecture

quicklogic/qlf_k4n8/techmap/cells_sim.v

@@ -20,24 +20,21 @@ module fpga_interconnect(datain, dataout);
 endmodule
 
 
-module frac_lut4_arith (\in[3] ,\in[2] ,\in[1] ,\in[0] ,cin, lut4_out, cout);
+module frac_lut4_arith (in ,cin, lut4_out, cout);
 
     parameter [15:0] LUT  = 16'd0;
     parameter [0: 0] MODE = 0;
 
-    input  [0:0] \in[3] ;
-    input  [0:0] \in[2] ;
-    input  [0:0] \in[1] ;
-    input  [0:0] \in[0] ;
+    input  [3:0] in;
     input  [0:0] cin;
     output [0:0] lut4_out;
     output [0:0] cout;
 
     // Mode bits of frac_lut4_arith are responsible for the LI2 mux which
     // selects between the LI2 and CIN inputs.
     wire [3:0] li = (MODE == 1'b1) ?
-        {\in[3] ,cin,    \in[1] ,\in[0] } :
-        {\in[3] ,\in[2] ,\in[1] ,\in[0] };
+        {in[3], cin, in[1], in[0]} :
+        {in[3], in[2], in[1], in[0]};
 
     // Output function
     wire [7:0] s1 = li[0] ?
@@ -60,15 +57,7 @@ module frac_lut4_arith (\in[3] ,\in[2] ,\in[1] ,\in[0] ,cin, lut4_out, cout);
     // Timing paths. The values are dummy and are intended to be replaced by
     // ones from a SDF file during simulation.
     specify
-        (\in[0] => lut4_out) = 0;
-        (\in[1] => lut4_out) = 0;
-        (\in[2] => lut4_out) = 0;
-        (\in[3] => lut4_out) = 0;
         (cin => lut4_out) = 0;
-        (\in[0] => cout) = 0;
-        (\in[1] => cout) = 0;
-        (\in[2] => cout) = 0;
-        (\in[3] => cout) = 0;
         (cin => cout) = 0;
     endspecify
 

quicklogic/qlf_k4n8/tests/features/post_synthesis_comb/CMakeLists.txt

@@ -3,7 +3,7 @@ set(QLF_K4N8_UMC22 qlf_k4n8-qlf_k4n8_umc22_fast)
 set(MULT_TB ${CMAKE_CURRENT_SOURCE_DIR}/multiplier_8bit_tb.v)
 
 set(CELLS_SIM ${CMAKE_CURRENT_SOURCE_DIR}/../../../techmap/cells_sim.v)
-set(POST_SYNTH_FILE ${CMAKE_CURRENT_BINARY_DIR}/multiplier_8bit_test4-umc22-adder/qlf_k4n8-${QLF_K4N8_UMC22}-virt-${QLF_K4N8_UMC22}-${QLF_K4N8_UMC22}/multiplier_8bit_post_synthesis.v)
+set(POST_SYNTH_FILE ${CMAKE_CURRENT_BINARY_DIR}/multiplier_8bit_test4-umc22-adder/qlf_k4n8-${QLF_K4N8_UMC22}-virt-${QLF_K4N8_UMC22}-${QLF_K4N8_UMC22}/multiplier_8bit_merged_post_implementation.v)
 
 add_fpga_target(
   NAME multiplier_8bit_test4-umc22-adder

quicklogic/qlf_k4n8/tests/features/post_synthesis_comb/multiplier_8bit_tb.v

@@ -8,7 +8,9 @@ module multiplier_8bit_tb( );
     reg status; 
 
     multiplier_8bit DUT (
-        .\a_in[0] (x0[0]), .\a_in[1] (x0[1]), .\a_in[2] (x0[2]), .\a_in[3] (x0[3]), .\a_in[4] (x0[4]), .\a_in[5] (x0[5]), .\a_in[6] (x0[6]), .\a_in[7] (x0[7]), .\b_in[0] (y0[0]), .\b_in[1] (y0[1]), .\b_in[2] (y0[2]), .\b_in[3] (y0[3]), .\b_in[4] (y0[4]), .\b_in[5] (y0[5]), .\b_in[6] (y0[6]), .\b_in[7] (y0[7]),	.\prod[0] (mult_out[0]), .\prod[1] (mult_out[1]), .\prod[2] (mult_out[2]), .\prod[3] (mult_out[3]), .\prod[4] (mult_out[4]), .\prod[5] (mult_out[5]), .\prod[6] (mult_out[6]), .\prod[7] (mult_out[7]), .\prod[8] (mult_out[8]), .\prod[9] (mult_out[9]), .\prod[10] (mult_out[10]), .\prod[11] (mult_out[11]), .\prod[12] (mult_out[12]), .\prod[13] (mult_out[13]), .\prod[14] (mult_out[14]), .\prod[15] (mult_out[15]));
+        .a_in(x0),
+	.b_in(y0),
+	.prod(mult_out));
 
     initial begin
 	    status = 0;

quicklogic/qlf_k4n8/tests/features/post_synthesis_seq/CMakeLists.txt

@@ -3,7 +3,7 @@ set(QLF_K4N8_UMC22 qlf_k4n8-qlf_k4n8_umc22_slow)
 set(COUNTER_TB ${CMAKE_CURRENT_SOURCE_DIR}/counter_16bit_tb.v)
 
 set(CELLS_SIM ${CMAKE_CURRENT_SOURCE_DIR}/../../../techmap/cells_sim.v)
-set(POST_SYNTH_FILE ${CMAKE_CURRENT_BINARY_DIR}/counter_16bit_test4-umc22-adder/qlf_k4n8-${QLF_K4N8_UMC22}-virt-${QLF_K4N8_UMC22}-${QLF_K4N8_UMC22}/top_post_synthesis.v)
+set(POST_SYNTH_FILE ${CMAKE_CURRENT_BINARY_DIR}/counter_16bit_test4-umc22-adder/qlf_k4n8-${QLF_K4N8_UMC22}-virt-${QLF_K4N8_UMC22}-${QLF_K4N8_UMC22}/top_merged_post_implementation.v)
 
 add_fpga_target(
   NAME counter_16bit_test4-umc22-adder

quicklogic/qlf_k4n8/tests/features/post_synthesis_seq/counter_16bit_tb.v

@@ -15,7 +15,11 @@ module counter_16bit_tb;
 
 reg [15:0] count_compare; 
 
-top DUT (.clk(clk), .reset(reset), .enable(enable), .\count[0] (count[0]), .\count[1] (count[1]), .\count[2] (count[2]), .\count[3] (count[3]), .\count[4] (count[4]), .\count[5] (count[5]), .\count[6] (count[6]), .\count[7] (count[7]), .\count[8] (count[8]), .\count[9] (count[9]), .\count[10] (count[10]), .\count[11] (count[11]), .\count[12] (count[12]), .\count[13] (count[13]), .\count[14] (count[14]), .\count[15] (count[15]));
+top DUT (
+  .clk(clk),
+  .reset(reset),
+  .enable(enable),
+  .count(count));
 
 event terminate_sim;  
   initial begin