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phase in new CRC logic for loading (phase 1)
Summary: Transition to the correct way to compute the CRC32C checksum. # Initial Value and Final XOR The standard initial value for CRC32C is `0xFFFFFFFF` (not `0x04C11DB7`). Also the final XOR with `0xFFFFFFFF` was missing. CRC32C uses the polynomial `0x1EDC6F41`. Using the standard CRC32's `0x04C11DB7` polynomial as the initial value does not set that to the checksum's polynomial. # Argument Order Both the built-ins `__builtin_ia32_crc32di` and `_mm_crc32_u64` take (crc, v) not (v, crc). The high 32-bits from the 64-bit first argument will be ignored, which means we're not verifying those bits. ``` fbclock_crc64(0x12345678, 0xffffffff) = 0x399d2062 fbclock_crc64(0xffffffff, 0x12345678) = 0x399d2062 fbclock_crc64(0x1234567812345678, 0xffffffff) = 0x399d2062 fbclock_crc64(0xffffffff, 0x1234567812345678) = 0xc3e97656 ``` This means we need to swap the order of the arguments for `fbclock_crc64`. # Rollout To roll this fix out, we need to do it in three phases. Each phase must be fully rolled out before the next one can land. 1. Update loading to ensure all logic reading the CRC accepts both the old and new one. 2. Update storing to ensure all logic storing the CRC is using the new one. 3. Removed the deprecated second CRC check on loading. NOTE: This phase must be fully rolled out before landing the next phase. Reviewed By: abulimov Differential Revision: D43413687 fbshipit-source-id: 7145fe8ed1b3f19e0dd91ffee0495a2511e1e305
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