Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Enable connected ports, configure connectors and LLDP #114

Open
wants to merge 5 commits into
base: master
Choose a base branch
from
+48 −6
Open

Enable connected ports, configure connectors and LLDP #114

Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
a3ba111
Fix ixr-ec
jbemmel Nov 17, 2022
08e07a0
Merge branch 'hellt:master' into master
jbemmel Mar 29, 2023
3ab3e4e
Merge branch 'hellt:master' into master
jbemmel May 12, 2023
f68820a
Add provisioning of ports
jbemmel May 23, 2023
2396d36
Provision ports, connectors and LLDP
jbemmel May 23, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
54 changes: 48 additions & 6 deletions sros/docker/launch.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,7 @@ def line_card_config(
"deployment_model": "distributed",
# control plane (CPM)
"max_nics": 34, # 24*10 + 8*25G + 2*100G (with connector)
"connector": {"type": "c1-100g", "ports": [33, 34]},
"cp": {
"min_ram": 3,
"timos_line": "slot=A chassis=ixr-e card=cpm-ixr-e",
Expand Down Expand Up @@ -155,7 +156,7 @@ def line_card_config(
"ixr-e-small": {
"deployment_model": "distributed",
# control plane (CPM)
"max_nics": 18,
"max_nics": 18, # Note: vSIM supports max 8 NICs, up to 1/1/6
"cp": {
"min_ram": 3,
"timos_line": "slot=A chassis=ixr-e card=imm14-10g-sfp++4-1g-tx",
Expand Down Expand Up @@ -195,6 +196,7 @@ def line_card_config(
integrated=True,
),
"power": {"modules": {"ac/hv": 3, "dc": 4}},
"connector": {"type": "c1-100g"},
},
"sr-1s-macsec": {
"deployment_model": "integrated",
Expand All @@ -207,11 +209,13 @@ def line_card_config(
/configure card 1 xiom x1 mda 1 mda-type ms16-100gb-sfpdd+4-100gb-qsfp28
""",
"power": {"modules": {"ac/hv": 3, "dc": 4}},
"connector": { "type": "c1-100g", "xiom": True }, # TODO derive XIOM flag from timos_line
},
"sr-2s": {
"deployment_model": "distributed",
"max_nics": 10, # 8+2
"power": {"modules": {"ac/hv": 3, "dc": 4}},
"connector": {"type": "c1-100g", "xiom": True},
"cp": {
"min_ram": 3,
# The 7750 SR-2s uses an integrated switch fabric module (SFM) design
Expand All @@ -236,6 +240,7 @@ def line_card_config(
# control plane (CPM)
"max_nics": 36,
"power": {"modules": 10, "shelves": 2},
"connector": {"type": "c1-100g"},
"cp": {
"min_ram": 4,
"timos_line": "slot=A chassis=SR-7s sfm=sfm2-s card=cpm2-s",
Expand Down Expand Up @@ -290,6 +295,7 @@ def line_card_config(
# control plane (CPM)
"max_nics": 36,
"power": {"modules": 10, "shelves": 2},
"connector": {"type": "c1-100g"},
"cp": {
"min_ram": 4,
"timos_line": "slot=A chassis=SR-14s sfm=sfm-s card=cpm2-s",
Expand Down Expand Up @@ -326,6 +332,7 @@ def line_card_config(
mda="me12-100gb-qsfp28",
integrated=True,
),
"connector": {"type": "c1-100g"},
},
"sr-1e": {
"deployment_model": "distributed",
Expand Down Expand Up @@ -619,7 +626,7 @@ def gen_bof_config():


class SROS_vm(vrnetlab.VM):
def __init__(self, username, password, ram, conn_mode, cpu=2, num=0):
def __init__(self, username, password, ram, conn_mode, cpu=2, num=0, port_count=0):
super().__init__(username, password, disk_image="/sros.qcow2", num=num, ram=ram)
self.nic_type = "virtio-net-pci"
self.conn_mode = conn_mode
Expand All @@ -630,6 +637,7 @@ def __init__(self, username, password, ram, conn_mode, cpu=2, num=0):
cpu = 2
self.cpu = cpu
self.qemu_args.extend(["-cpu", "host", "-smp", f"{cpu}"])
self.port_count = port_count # Number of connected ports

def bootstrap_spin(self):
"""This function should be called periodically to do work."""
Expand Down Expand Up @@ -670,6 +678,32 @@ def bootstrap_spin(self):

return

def configure_ports(self):
"""
Enable all connected ports, provision connectors & enable LLDP
"""
for p in range(1, self.port_count + 1):
portname = f"port 1/1/{p}"
# Some mda's use 1/1/c for breakout, on some ports
# XIOM: 1/x1/1/c[n]/1
if "connector" in self.variant:
conn = self.variant["connector"]
if "ports" not in conn or p in conn["ports"]:
portname = f"port 1/{'x1/' if 'xiom' in conn else ''}1/c{p}"
self.wait_write(
f"/configure {portname} connector breakout {conn['type']}"
)
self.wait_write(f"/configure {portname} no shutdown")
portname += "/1" # Using only 1:1 breakout types

self.wait_write(
f"/configure {portname} ethernet lldp dest-mac nearest-bridge admin-status tx-rx"
)
self.wait_write(
f"/configure {portname} ethernet lldp dest-mac nearest-bridge tx-tlvs port-desc sys-name sys-desc"
)
self.wait_write(f"/configure {portname} no shutdown")

def read_license(self):
"""Read the license file, if it exists, and extract the UUID and start
time of the license
Expand Down Expand Up @@ -810,6 +844,9 @@ def bootstrap_config(self):
if "power" in self.variant:
self.configure_power(self.variant["power"])

# Enable connected ports including LLDP rx/tx
self.configure_ports()

self.commitConfig()

# configure bof
Expand All @@ -831,7 +868,7 @@ class SROS_integrated(SROS_vm):
"""Integrated VSR-SIM"""

def __init__(
self, hostname, username, password, mode, num_nics, variant, conn_mode
self, hostname, username, password, mode, num_nics, variant, conn_mode, port_count
):
ram: int = vrnetlab.getMem("integrated", variant.get("min_ram"))
cpu: int = vrnetlab.getCpu("integrated", variant.get("cpu"))
Expand All @@ -842,6 +879,7 @@ def __init__(
cpu=cpu,
ram=ram,
conn_mode=conn_mode,
port_count=port_count,
)
self.mode = mode
self.role = "integrated"
Expand Down Expand Up @@ -884,7 +922,7 @@ def gen_mgmt(self):
class SROS_cp(SROS_vm):
"""Control plane for distributed VSR-SIM"""

def __init__(self, hostname, username, password, mode, variant, conn_mode):
def __init__(self, hostname, username, password, mode, variant, conn_mode, port_count):
# cp - control plane. role is used to create a separate overlay image name
self.role = "cp"

Expand All @@ -897,6 +935,7 @@ def __init__(self, hostname, username, password, mode, variant, conn_mode):
cpu=cpu,
ram=ram,
conn_mode=conn_mode,
port_count=port_count,
)
self.mode = mode
self.num_nics = 0
Expand Down Expand Up @@ -1018,7 +1057,7 @@ def bootstrap_spin(self):

# SROS is main class for VSR-SIM
class SROS(vrnetlab.VR):
def __init__(self, hostname, username, password, mode, variant_name, conn_mode):
def __init__(self, hostname, username, password, mode, variant_name, conn_mode, port_count):
super().__init__(username, password)

if variant_name.lower() in SROS_VARIANTS:
Expand All @@ -1029,7 +1068,7 @@ def __init__(self, hostname, username, password, mode, variant_name, conn_mode):
parse_variant_line(lc.get("timos_line", ""), lc)
for lc in variant["lcs"]
]
variant["lsc"] = sort_lc_lines_by_slot(variant["lcs"])
variant["lcs"] = sort_lc_lines_by_slot(variant["lcs"])
else:
variant = parse_custom_variant(variant_name)

Expand Down Expand Up @@ -1065,6 +1104,7 @@ def __init__(self, hostname, username, password, mode, variant_name, conn_mode):
mode,
variant,
conn_mode,
port_count=port_count,
)
]

Expand Down Expand Up @@ -1129,6 +1169,7 @@ def __init__(self, hostname, username, password, mode, variant_name, conn_mode):
variant["max_nics"],
variant,
conn_mode=conn_mode,
port_count=port_count,
)
]

Expand Down Expand Up @@ -1309,5 +1350,6 @@ def getDefaultConfig() -> str:
mode=args.mode,
variant_name=args.variant,
conn_mode=args.connection_mode,
port_count=int(os.environ["CLAB_INTFS"]) if "CLAB_INTFS" in os.environ else 0,
)
ia.start(add_fwd_rules=False)