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10 Open 1 Closed
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Issues list

Runtime configurable memory latencies enhancement New feature or request
#29 opened May 15, 2022 by smosanu Integration
@smosanu
support for STT or other non-volatile memory model enhancement New feature or request
#28 opened May 15, 2022 by smosanu MEM
@ms3xy
tFAW and other global timings integrated into the memory model help wanted Extra attention is needed
#27 opened May 15, 2022 by smosanu MEM
@ms3xy
Interleaving testbenches are out of date enhancement New feature or request
#25 opened May 10, 2022 by smosanu MEM
@smosanu
Support for parity enhancement New feature or request
#24 opened May 9, 2022 by smosanu MEM
@smosanu
AXI bridge between board memory and DSync / model rows help wanted Extra attention is needed
#23 opened May 9, 2022 by smosanu Integration
@smosanu
Optimize Fmax enhancement New feature or request
#22 opened May 9, 2022 by smosanu Integration
@smosanu
Use DQS signals enhancement New feature or request
#21 opened May 9, 2022 by smosanu MEM
@smosanu
Use ODT signal enhancement New feature or request
#20 opened May 9, 2022 by smosanu MEM
@smosanu
Rank is not supported correctly enhancement New feature or request
#15 opened Jan 25, 2022 by smosanu MEM
@smosanu
1
ProTip! Exclude everything labeled bug with -label:bug.