[SYCL][FPGA][NFC] Update disable_loop_pipelining attribute (#5080)

This patch simplifies support for disable_loop_pipelining attribute by setting SimpleHandler = 1 in Attr.td instead of using static handler function in SemaDeclAttr.cpp file. This behavior is more consistent and aligns with other community attributes. No functionality or tests change with the improvement. Signed-off-by: Soumi Manna <[email protected]>
intel · Dec 4, 2021 · 3b1ba34 · 3b1ba34
1 parent 5ce99b8
commit 3b1ba34
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Showing 2 changed files with 1 addition and 10 deletions.
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
@@ -2024,6 +2024,7 @@ def SYCLIntelFPGADisableLoopPipelining : DeclOrStmtAttr {
   let IsStmtDependent = 1;
   let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
   let SupportsNonconformingLambdaSyntax = 1;
+  let SimpleHandler = 1;
 }
 def : MutualExclusions<[SYCLIntelFPGAInitiationInterval,
                         SYCLIntelFPGADisableLoopPipelining]>;

diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -3566,13 +3566,6 @@ static void handleSYCLIntelUseStallEnableClustersAttr(Sema &S, Decl *D,
                  SYCLIntelUseStallEnableClustersAttr(S.Context, A));
 }
 
-// Handles disable_loop_pipelining attribute.
-static void handleSYCLIntelFPGADisableLoopPipeliningAttr(Sema &S, Decl *D,
-                                                         const ParsedAttr &A) {
-  D->addAttr(::new (S.Context)
-                 SYCLIntelFPGADisableLoopPipeliningAttr(S.Context, A));
-}
-
 // Handles initiation_interval attribute.
 void Sema::AddSYCLIntelFPGAInitiationIntervalAttr(Decl *D,
                                                   const AttributeCommonInfo &CI,
@@ -9976,9 +9969,6 @@ static void ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D,
   case ParsedAttr::AT_SYCLIntelLoopFuse:
     handleSYCLIntelLoopFuseAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_SYCLIntelFPGADisableLoopPipelining:
-    handleSYCLIntelFPGADisableLoopPipeliningAttr(S, D, AL);
-    break;
   case ParsedAttr::AT_SYCLIntelFPGAInitiationInterval:
     handleSYCLIntelFPGAInitiationIntervalAttr(S, D, AL);
     break;