Skip to content

Commit

Permalink
update memory test check; add round trip test for creating new top le…
Browse files Browse the repository at this point in the history 
…vel function
  • Loading branch information
@jiahanxie353
jiahanxie353 committed Nov 1, 2024
1 parent a771cc2 commit 1a33416
Show file tree
Hide file tree
Showing 2 changed files with 117 additions and 30 deletions.
60 changes: 30 additions & 30 deletions test/Conversion/SCFToCalyx/convert_memory.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -372,7 +372,7 @@ module {
// External memory store.

module {
// CHECK-LABEL: calyx.component @main_1(
// CHECK-LABEL: calyx.component @main(
// CHECK-SAME: %[[VAL_0:in0]]: i32,
// CHECK-SAME: %[[VAL_1:in1]]: i32,
// CHECK-SAME: %[[VAL_2:.*]]: i1 {clk},
Expand All @@ -381,23 +381,23 @@ module {
// CHECK-SAME: %[[VAL_5:.*]]: i1 {done}) {
// CHECK: %[[VAL_6:.*]] = hw.constant true
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]], %[[VAL_9:.*]], %[[VAL_10:.*]], %[[VAL_11:.*]], %[[VAL_12:.*]], %[[VAL_13:.*]], %[[VAL_14:.*]] = calyx.seq_mem @mem_0 <[8] x 32> [3] {external = true} : i3, i1, i1, i1, i1, i32, i32, i1
// CHECK: %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]], %[[VAL_18:.*]], %[[VAL_19:.*]], %[[VAL_20:.*]] = calyx.instance @main_instance of @main : i32, i32, i1, i1, i1, i1
// CHECK: %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]], %[[VAL_18:.*]], %[[VAL_19:.*]], %[[VAL_20:.*]] = calyx.instance @main_1_instance of @main_1 : i32, i32, i1, i1, i1, i1
// CHECK: calyx.wires {
// CHECK: calyx.group @init_main_instance {
// CHECK: calyx.group @init_main_1_instance {
// CHECK: calyx.assign %[[VAL_18]] = %[[VAL_6]] : i1
// CHECK: calyx.assign %[[VAL_19]] = %[[VAL_6]] : i1
// CHECK: calyx.group_done %[[VAL_20]] : i1
// CHECK: }
// CHECK: }
// CHECK: calyx.control {
// CHECK: calyx.seq {
// CHECK: calyx.enable @init_main_instance
// CHECK: calyx.invoke @main_instance[arg_mem_0 = mem_0](%[[VAL_15]] = %[[VAL_0]], %[[VAL_16]] = %[[VAL_1]]) -> (i32, i32)
// CHECK: calyx.enable @init_main_1_instance
// CHECK: calyx.invoke @main_1_instance[arg_mem_0 = mem_0](%[[VAL_15]] = %[[VAL_0]], %[[VAL_16]] = %[[VAL_1]]) -> (i32, i32)
// CHECK: }
// CHECK: }
// CHECK: } {toplevel}

// CHECK-LABEL: calyx.component @main(
// CHECK-LABEL: calyx.component @main_1(
// CHECK-SAME: %[[VAL_0:in0]]: i32,
// CHECK-SAME: %[[VAL_1:in2]]: i32,
// CHECK-SAME: %[[VAL_2:.*]]: i1 {clk},
Expand Down Expand Up @@ -434,31 +434,31 @@ module {
// External memory load.

module {
// CHECK-LABEL: calyx.component @main_1(
// CHECK-LABEL: calyx.component @main(
// CHECK-SAME: %[[VAL_0:.*]]: i32,
// CHECK-SAME: %[[VAL_1:.*]]: i1 {clk},
// CHECK-SAME: %[[VAL_2:.*]]: i1 {reset},
// CHECK-SAME: %[[VAL_3:.*]]: i1 {go}) -> (
// CHECK-SAME: %[[VAL_4:.*]]: i1 {done}) {
// CHECK: %[[VAL_5:.*]] = hw.constant true
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]], %[[VAL_8:.*]], %[[VAL_9:.*]], %[[VAL_10:.*]], %[[VAL_11:.*]], %[[VAL_12:.*]], %[[VAL_13:.*]] = calyx.seq_mem @mem_0 <[8] x 32> [3] {external = true} : i3, i1, i1, i1, i1, i32, i32, i1
// CHECK: %[[VAL_14:.*]], %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]], %[[VAL_18:.*]], %[[VAL_19:.*]] = calyx.instance @main_instance of @main : i32, i1, i1, i1, i32, i1
// CHECK: %[[VAL_14:.*]], %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]], %[[VAL_18:.*]], %[[VAL_19:.*]] = calyx.instance @main_1_instance of @main_1 : i32, i1, i1, i1, i32, i1
// CHECK: calyx.wires {
// CHECK: calyx.group @init_main_instance {
// CHECK: calyx.group @init_main_1_instance {
// CHECK: calyx.assign %[[VAL_16]] = %[[VAL_5]] : i1
// CHECK: calyx.assign %[[VAL_17]] = %[[VAL_5]] : i1
// CHECK: calyx.group_done %[[VAL_19]] : i1
// CHECK: }
// CHECK: }
// CHECK: calyx.control {
// CHECK: calyx.seq {
// CHECK: calyx.enable @init_main_instance
// CHECK: calyx.invoke @main_instance[arg_mem_0 = mem_0](%[[VAL_14]] = %[[VAL_0]]) -> (i32)
// CHECK: calyx.enable @init_main_1_instance
// CHECK: calyx.invoke @main_1_instance[arg_mem_0 = mem_0](%[[VAL_14]] = %[[VAL_0]]) -> (i32)
// CHECK: }
// CHECK: }
// CHECK: } {toplevel}

// CHECK-LABEL: calyx.component @main(
// CHECK-LABEL: calyx.component @main_1(
// CHECK-SAME: %[[VAL_0:in0]]: i32,
// CHECK-SAME: %[[VAL_1:.*]]: i1 {clk},
// CHECK-SAME: %[[VAL_2:.*]]: i1 {reset},
Expand Down Expand Up @@ -503,7 +503,7 @@ module {
// External memory hazard.

module {
// CHECK-LABEL: calyx.component @main_1(
// CHECK-LABEL: calyx.component @main(
// CHECK-SAME: %[[VAL_0:in0]]: i32,
// CHECK-SAME: %[[VAL_1:in1]]: i32,
// CHECK-SAME: %[[VAL_2:.*]]: i1 {clk},
Expand All @@ -512,23 +512,23 @@ module {
// CHECK-SAME: %[[VAL_5:.*]]: i1 {done}) {
// CHECK: %[[VAL_6:.*]] = hw.constant true
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]], %[[VAL_9:.*]], %[[VAL_10:.*]], %[[VAL_11:.*]], %[[VAL_12:.*]], %[[VAL_13:.*]], %[[VAL_14:.*]] = calyx.seq_mem @mem_0 <[8] x 32> [3] {external = true} : i3, i1, i1, i1, i1, i32, i32, i1
// CHECK: %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]], %[[VAL_18:.*]], %[[VAL_19:.*]], %[[VAL_20:.*]], %[[VAL_21:.*]], %[[VAL_22:.*]] = calyx.instance @main_instance of @main : i32, i32, i1, i1, i1, i32, i32, i1
// CHECK: %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]], %[[VAL_18:.*]], %[[VAL_19:.*]], %[[VAL_20:.*]], %[[VAL_21:.*]], %[[VAL_22:.*]] = calyx.instance @main_1_instance of @main_1 : i32, i32, i1, i1, i1, i32, i32, i1
// CHECK: calyx.wires {
// CHECK: calyx.group @init_main_instance {
// CHECK: calyx.group @init_main_1_instance {
// CHECK: calyx.assign %[[VAL_18]] = %[[VAL_6]] : i1
// CHECK: calyx.assign %[[VAL_19]] = %[[VAL_6]] : i1
// CHECK: calyx.group_done %[[VAL_22]] : i1
// CHECK: }
// CHECK: }
// CHECK: calyx.control {
// CHECK: calyx.seq {
// CHECK: calyx.enable @init_main_instance
// CHECK: calyx.invoke @main_instance[arg_mem_0 = mem_0](%[[VAL_15]] = %[[VAL_0]], %[[VAL_16]] = %[[VAL_1]]) -> (i32, i32)
// CHECK: calyx.enable @init_main_1_instance
// CHECK: calyx.invoke @main_1_instance[arg_mem_0 = mem_0](%[[VAL_15]] = %[[VAL_0]], %[[VAL_16]] = %[[VAL_1]]) -> (i32, i32)
// CHECK: }
// CHECK: }
// CHECK: } {toplevel}

// CHECK-LABEL: calyx.component @main(
// CHECK-LABEL: calyx.component @main_1(
// CHECK-SAME: %[[VAL_0:in0]]: i32,
// CHECK-SAME: %[[VAL_1:in1]]: i32,
// CHECK-SAME: %[[VAL_2:.*]]: i1 {clk},
Expand Down Expand Up @@ -658,30 +658,30 @@ module {
// Load from memory with more elements than index width (32 bits).

module {
// CHECK-LABEL: calyx.component @main_1(
// CHECK-LABEL: calyx.component @main(
// CHECK-SAME: %[[VAL_0:.*]]: i1 {clk},
// CHECK-SAME: %[[VAL_1:.*]]: i1 {reset},
// CHECK-SAME: %[[VAL_2:.*]]: i1 {go}) -> (
// CHECK-SAME: %[[VAL_3:.*]]: i1 {done}) {
// CHECK: %[[VAL_4:.*]] = hw.constant true
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]], %[[VAL_7:.*]], %[[VAL_8:.*]], %[[VAL_9:.*]], %[[VAL_10:.*]], %[[VAL_11:.*]], %[[VAL_12:.*]] = calyx.seq_mem @mem_0 <[33] x 32> [6] {external = true} : i6, i1, i1, i1, i1, i32, i32, i1
// CHECK: %[[VAL_13:.*]], %[[VAL_14:.*]], %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]] = calyx.instance @main_instance of @main : i1, i1, i1, i32, i1
// CHECK: %[[VAL_13:.*]], %[[VAL_14:.*]], %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]] = calyx.instance @main_1_instance of @main_1 : i1, i1, i1, i32, i1
// CHECK: calyx.wires {
// CHECK: calyx.group @init_main_instance {
// CHECK: calyx.group @init_main_1_instance {
// CHECK: calyx.assign %[[VAL_14]] = %[[VAL_4]] : i1
// CHECK: calyx.assign %[[VAL_15]] = %[[VAL_4]] : i1
// CHECK: calyx.group_done %[[VAL_17]] : i1
// CHECK: }
// CHECK: }
// CHECK: calyx.control {
// CHECK: calyx.seq {
// CHECK: calyx.enable @init_main_instance
// CHECK: calyx.invoke @main_instance[arg_mem_0 = mem_0]() -> ()
// CHECK: calyx.enable @init_main_1_instance
// CHECK: calyx.invoke @main_1_instance[arg_mem_0 = mem_0]() -> ()
// CHECK: }
// CHECK: }
// CHECK: } {toplevel}

// CHECK-LABEL: calyx.component @main(
// CHECK-LABEL: calyx.component @main_1(
// CHECK-SAME: %[[VAL_0:.*]]: i1 {clk},
// CHECK-SAME: %[[VAL_1:.*]]: i1 {reset},
// CHECK-SAME: %[[VAL_2:.*]]: i1 {go}) -> (
Expand Down Expand Up @@ -814,31 +814,31 @@ module {

// Original top-level function's alloc-memories should be passed by reference
module {
// CHECK-LABEL: calyx.component @main_1(
// CHECK-LABEL: calyx.component @main(
// CHECK-SAME: %[[VAL_0:.*]]: i1 {clk},
// CHECK-SAME: %[[VAL_1:.*]]: i1 {reset},
// CHECK-SAME: %[[VAL_2:.*]]: i1 {go}) -> (
// CHECK-SAME: %[[VAL_3:.*]]: i1 {done}) {
// CHECK: %[[VAL_4:.*]] = hw.constant true
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]], %[[VAL_7:.*]], %[[VAL_8:.*]], %[[VAL_9:.*]], %[[VAL_10:.*]], %[[VAL_11:.*]], %[[VAL_12:.*]] = calyx.seq_mem @mem_1 <[1] x 32> [1] {external = true} : i1, i1, i1, i1, i1, i32, i32, i1
// CHECK: %[[VAL_13:.*]], %[[VAL_14:.*]], %[[VAL_15:.*]], %[[VAL_16:.*]], %[[VAL_17:.*]], %[[VAL_18:.*]], %[[VAL_19:.*]], %[[VAL_20:.*]] = calyx.seq_mem @mem_0 <[1] x 32> [1] {external = true} : i1, i1, i1, i1, i1, i32, i32, i1
// CHECK: %[[VAL_21:.*]], %[[VAL_22:.*]], %[[VAL_23:.*]], %[[VAL_24:.*]], %[[VAL_25:.*]] = calyx.instance @main_instance of @main : i1, i1, i1, i32, i1
// CHECK: %[[VAL_21:.*]], %[[VAL_22:.*]], %[[VAL_23:.*]], %[[VAL_24:.*]], %[[VAL_25:.*]] = calyx.instance @main_1_instance of @main_1 : i1, i1, i1, i32, i1
// CHECK: calyx.wires {
// CHECK: calyx.group @init_main_instance {
// CHECK: calyx.group @init_main_1_instance {
// CHECK: calyx.assign %[[VAL_22]] = %[[VAL_4]] : i1
// CHECK: calyx.assign %[[VAL_23]] = %[[VAL_4]] : i1
// CHECK: calyx.group_done %[[VAL_25]] : i1
// CHECK: }
// CHECK: }
// CHECK: calyx.control {
// CHECK: calyx.seq {
// CHECK: calyx.enable @init_main_instance
// CHECK: calyx.invoke @main_instance[arg_mem_0 = mem_0, arg_mem_1 = mem_1]() -> ()
// CHECK: calyx.enable @init_main_1_instance
// CHECK: calyx.invoke @main_1_instance[arg_mem_0 = mem_0, arg_mem_1 = mem_1]() -> ()
// CHECK: }
// CHECK: }
// CHECK: } {toplevel}

// CHECK-LABEL: calyx.component @main(
// CHECK-LABEL: calyx.component @main_1(
// CHECK-SAME: %[[VAL_0:.*]]: i1 {clk},
// CHECK-SAME: %[[VAL_1:.*]]: i1 {reset},
// CHECK-SAME: %[[VAL_2:.*]]: i1 {go}) -> (
Expand Down
87 changes: 87 additions & 0 deletions test/Dialect/Calyx/round-trip.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -444,3 +444,90 @@ module attributes {calyx.entrypoint = "main"} {
}
}
}

// -----

module attributes {calyx.entrypoint = "main"} {
// CHECK-LABEL: calyx.component @main(%in0: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%done: i1 {done}) {
calyx.component @main(%in0: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%done: i1 {done}) {
%true = hw.constant true
%mem_1.addr0, %mem_1.clk, %mem_1.reset, %mem_1.content_en, %mem_1.write_en, %mem_1.write_data, %mem_1.read_data, %mem_1.done = calyx.seq_mem @mem_1 <[8] x 32> [3] {external = true} : i3, i1, i1, i1, i1, i32, i32, i1
%mem_0.addr0, %mem_0.clk, %mem_0.reset, %mem_0.content_en, %mem_0.write_en, %mem_0.write_data, %mem_0.read_data, %mem_0.done = calyx.seq_mem @mem_0 <[8] x 32> [3] {external = true} : i3, i1, i1, i1, i1, i32, i32, i1
%main_1_instance.in1, %main_1_instance.clk, %main_1_instance.reset, %main_1_instance.go, %main_1_instance.done = calyx.instance @main_1_instance of @main_1 : i32, i1, i1, i1, i1
calyx.wires {
calyx.group @init_main_1_instance {
calyx.assign %main_1_instance.reset = %true : i1
calyx.assign %main_1_instance.go = %true : i1
calyx.group_done %main_1_instance.done : i1
}
}
calyx.control {
calyx.seq {
calyx.seq {
calyx.enable @init_main_1_instance
// CHECK: calyx.invoke @main_1_instance[arg_mem_0 = mem_0, arg_mem_1 = mem_1](%main_1_instance.in1 = %in0) -> (i32)
calyx.invoke @main_1_instance[arg_mem_0 = mem_0, arg_mem_1 = mem_1](%main_1_instance.in1 = %in0) -> (i32)
}
}
}
} {toplevel}
// CHECK-LABEL: calyx.component @main_1(%in1: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%done: i1 {done}) {
calyx.component @main_1(%in1: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%done: i1 {done}) {
%true = hw.constant true
%c1_i32 = hw.constant 1 : i32
%func_1_instance.in0, %func_1_instance.in2, %func_1_instance.clk, %func_1_instance.reset, %func_1_instance.go, %func_1_instance.done = calyx.instance @func_1_instance of @func_1 : i32, i32, i1, i1, i1, i1
%arg_mem_1.addr0, %arg_mem_1.clk, %arg_mem_1.reset, %arg_mem_1.content_en, %arg_mem_1.write_en, %arg_mem_1.write_data, %arg_mem_1.read_data, %arg_mem_1.done = calyx.seq_mem @arg_mem_1 <[8] x 32> [3] : i3, i1, i1, i1, i1, i32, i32, i1
%arg_mem_0.addr0, %arg_mem_0.clk, %arg_mem_0.reset, %arg_mem_0.content_en, %arg_mem_0.write_en, %arg_mem_0.write_data, %arg_mem_0.read_data, %arg_mem_0.done = calyx.seq_mem @arg_mem_0 <[8] x 32> [3] : i3, i1, i1, i1, i1, i32, i32, i1
calyx.wires {
calyx.group @init_func_1_instance {
calyx.assign %func_1_instance.reset = %true : i1
calyx.assign %func_1_instance.go = %true : i1
calyx.group_done %func_1_instance.done : i1
}
}
calyx.control {
calyx.seq {
calyx.seq {
calyx.enable @init_func_1_instance
// CHECK: calyx.invoke @func_1_instance[arg_mem_0 = arg_mem_0, arg_mem_1 = arg_mem_1](%func_1_instance.in0 = %c1_i32, %func_1_instance.in2 = %in1) -> (i32, i32)
calyx.invoke @func_1_instance[arg_mem_0 = arg_mem_0, arg_mem_1 = arg_mem_1](%func_1_instance.in0 = %c1_i32, %func_1_instance.in2 = %in1) -> (i32, i32)
}
}
}
}
// CHECK-LABEL: calyx.component @func_1(%in0: i32, %in2: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%done: i1 {done}) {
calyx.component @func_1(%in0: i32, %in2: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%done: i1 {done}) {
%true = hw.constant true
%std_slice_1.in, %std_slice_1.out = calyx.std_slice @std_slice_1 : i32, i3
%std_slice_0.in, %std_slice_0.out = calyx.std_slice @std_slice_0 : i32, i3
%arg_mem_1.addr0, %arg_mem_1.clk, %arg_mem_1.reset, %arg_mem_1.content_en, %arg_mem_1.write_en, %arg_mem_1.write_data, %arg_mem_1.read_data, %arg_mem_1.done = calyx.seq_mem @arg_mem_1 <[8] x 32> [3] : i3, i1, i1, i1, i1, i32, i32, i1
%arg_mem_0.addr0, %arg_mem_0.clk, %arg_mem_0.reset, %arg_mem_0.content_en, %arg_mem_0.write_en, %arg_mem_0.write_data, %arg_mem_0.read_data, %arg_mem_0.done = calyx.seq_mem @arg_mem_0 <[8] x 32> [3] : i3, i1, i1, i1, i1, i32, i32, i1
calyx.wires {
calyx.group @bb0_0 {
calyx.assign %std_slice_1.in = %in2 : i32
calyx.assign %arg_mem_1.addr0 = %std_slice_1.out : i3
calyx.assign %arg_mem_1.write_data = %in0 : i32
calyx.assign %arg_mem_1.write_en = %true : i1
calyx.assign %arg_mem_1.content_en = %true : i1
calyx.group_done %arg_mem_1.done : i1
}
calyx.group @bb0_1 {
calyx.assign %std_slice_0.in = %in2 : i32
calyx.assign %arg_mem_0.addr0 = %std_slice_0.out : i3
calyx.assign %arg_mem_0.write_data = %in0 : i32
calyx.assign %arg_mem_0.write_en = %true : i1
calyx.assign %arg_mem_0.content_en = %true : i1
calyx.group_done %arg_mem_0.done : i1
}
}
calyx.control {
calyx.seq {
calyx.seq {
calyx.enable @bb0_0
calyx.enable @bb0_1
}
}
}
}
}

0 comments on commit 1a33416

Please sign in to comment.