Merge remote-tracking branch 'upstream/main' into mingzhe-structRef

frontends/PyCDE/src/pycde/constructs.py

@@ -34,6 +34,9 @@ def NamedWire(type_or_value: Union[Type, Signal], name: str):
 
   class NamedWire(type._get_value_class()):
 
+    if not type.is_hw_type:
+      raise TypeError(f"NamedWire must have a hardware type, not {type}")
+
     def __init__(self):
       self.assigned_value = None
       # TODO: We assume here that names are unique within a module, which isn't

frontends/PyCDE/src/pycde/types.py

@@ -87,6 +87,10 @@ def strip(self):
   def bitwidth(self):
     return hw.get_bitwidth(self._type)
 
+  @property
+  def is_hw_type(self) -> bool:
+    assert False, "Subclass must override this method"
+
   def __call__(self, obj, name: str = None) -> "Signal":
     """Create a Value of this type from a python object."""
     assert not isinstance(
@@ -175,6 +179,10 @@ def __new__(cls, element_type: Type):
   def element_type(self) -> Type:
     return _FromCirctType(self._type.element_type)
 
+  @property
+  def is_hw_type(self) -> bool:
+    return True
+
   def _get_value_class(self):
     from .signals import InOutSignal
     return InOutSignal
@@ -205,6 +213,10 @@ def __new__(cls, inner_type: Type, name: str):
 
     return super(TypeAlias, cls).__new__(cls, alias, incl_cls_in_key=False)
 
+  @property
+  def is_hw_type(self) -> bool:
+    return self.inner_type.is_hw_type
+
   @staticmethod
   def declare_aliases(mod):
     if TypeAlias.RegisteredAliases is None:
@@ -291,6 +303,10 @@ def inner_type(self):
   def element_type(self):
     return _FromCirctType(self._type.element_type)
 
+  @property
+  def is_hw_type(self) -> bool:
+    return True
+
   @property
   def size(self):
     return self._type.size
@@ -345,6 +361,10 @@ def __new__(
     return super(StructType, cls).__new__(
         cls, hw.StructType.get([(n, t._type) for (n, t) in fields]))
 
+  @property
+  def is_hw_type(self) -> bool:
+    return True
+
   @property
   def fields(self):
     return [(n, _FromCirctType(t)) for n, t in self._type.get_fields()]
@@ -408,13 +428,21 @@ def __call__(self, **kwargs):
   def _get_value_class(self):
     return self._value_class
 
+  @property
+  def is_hw_type(self) -> bool:
+    return True
+
 
 class BitVectorType(Type):
 
   @property
   def width(self):
     return self._type.width
 
+  @property
+  def is_hw_type(self) -> bool:
+    return True
+
   def _from_obj_check(self, x):
     """This functionality can be shared by all the int types."""
     if not isinstance(x, int):
@@ -498,6 +526,10 @@ class ClockType(Type):
   def __new__(cls):
     return super(ClockType, cls).__new__(cls, seq.ClockType.get())
 
+  @property
+  def is_hw_type(self) -> bool:
+    return False
+
   def _get_value_class(self):
     from .signals import ClockSignal
     return ClockSignal
@@ -511,6 +543,10 @@ class Any(Type):
   def __new__(cls):
     return super(Any, cls).__new__(cls, esi.AnyType.get())
 
+  @property
+  def is_hw_type(self) -> bool:
+    return False
+
 
 class Channel(Type):
   """An ESI channel type."""
@@ -531,6 +567,10 @@ def __new__(cls,
   def inner_type(self):
     return _FromCirctType(self._type.inner)
 
+  @property
+  def is_hw_type(self) -> bool:
+    return False
+
   @property
   def signaling(self):
     return self._type.signaling
@@ -604,6 +644,10 @@ def _get_value_class(self):
     from .signals import BundleSignal
     return BundleSignal
 
+  @property
+  def is_hw_type(self) -> bool:
+    return False
+
   @property
   def channels(self):
     return [
@@ -720,6 +764,10 @@ def __new__(cls, element_type: Type):
   def element_type(self):
     return _FromCirctType(self._type.element_type)
 
+  @property
+  def is_hw_type(self) -> bool:
+    return False
+
   @property
   def _get_value_class(self):
     from .signals import ListSignal

frontends/PyCDE/test/test_constructs_errors.py

@@ -2,8 +2,9 @@
 
 from pycde import generator, types, Module
 from pycde.common import Clock, Input
-from pycde.constructs import Reg, Wire
+from pycde.constructs import NamedWire, Reg, Wire
 from pycde.testing import unittestmodule
+from pycde.types import Channel, UInt
 
 
 @unittestmodule()
@@ -61,3 +62,15 @@ def create(ports):
     r.assign(ports.In)
     # CHECK: ValueError: Cannot assign value to Reg twice.
     r.assign(ports.In)
+
+
+# -----
+
+
+@unittestmodule()
+class NamedWireHWError(Module):
+
+  @generator
+  def create(ports):
+    # CHECK: TypeError: NamedWire must have a hardware type, not Channel<UInt<32>, ValidReady>
+    NamedWire(Channel(UInt(32)), "asdf")

include/circt/Dialect/Moore/MooreOps.td

@@ -199,6 +199,7 @@ def VariableOp : MooreOp<"variable", [
     `` custom<ImplicitSSAName>($name) ($initial^)? attr-dict
     `:` type($result)
   }];
+  let hasCanonicalizeMethod = true;
 }
 
 def NetKindAttr : I32EnumAttr<"NetKind", "Net type kind", [
@@ -250,11 +251,24 @@ def NetOp : MooreOp<"net", [
   );
   let results = (outs Res<RefType, "", [MemAlloc]>:$result);
   let assemblyFormat = [{
-    ``custom<ImplicitSSAName>($name) $kind ($assignment^)? attr-dict
+    `` custom<ImplicitSSAName>($name) $kind ($assignment^)? attr-dict
     `:` type($result)
   }];
 }
 
+def AssignedVarOp : MooreOp<"assigned_variable", [
+  DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
+  TypesMatchWith<"initial value and variable types match",
+    "result", "initial", "cast<RefType>($_self).getNestedType()">
+]> {
+  let summary = "The copy of variable must have the initial value";
+  let arguments = (ins StrAttr:$name, UnpackedType:$initial);
+  let results = (outs Res<RefType, "", [MemAlloc]>:$result);
+  let assemblyFormat = [{
+    `` custom<ImplicitSSAName>($name) $initial attr-dict `:` type($result)
+  }];
+}
+
 def ReadOp : MooreOp<"read", [
   DeclareOpInterfaceMethods<PromotableMemOpInterface>,
   TypesMatchWith<"input and result types match",

lib/Dialect/Moore/MooreOps.cpp

@@ -266,6 +266,27 @@ VariableOp::handlePromotionComplete(const MemorySlot &slot, Value defaultValue,
   this->erase();
   return std::nullopt;
 }
+LogicalResult VariableOp::canonicalize(VariableOp op,
+                                       ::mlir::PatternRewriter &rewriter) {
+  Value initial;
+  for (auto *user : op->getUsers())
+    if (isa<ContinuousAssignOp>(user) &&
+        (user->getOperand(0) == op.getResult())) {
+      // Don't canonicalize the multiple continuous assignment to the same
+      // variable.
+      if (initial)
+        return failure();
+      initial = user->getOperand(1);
+    }
+
+  if (initial) {
+    rewriter.replaceOpWithNewOp<AssignedVarOp>(op, op.getType(), op.getName(),
+                                               initial);
+    return success();
+  }
+
+  return failure();
+}
 
 SmallVector<DestructurableMemorySlot> VariableOp::getDestructurableSlots() {
   if (isa<SVModuleOp>(getOperation()->getParentOp()))
@@ -324,7 +345,6 @@ VariableOp::handleDestructuringComplete(const DestructurableMemorySlot &slot,
   this->erase();
   return std::nullopt;
 }
-
 //===----------------------------------------------------------------------===//
 // NetOp
 //===----------------------------------------------------------------------===//
@@ -333,6 +353,14 @@ void NetOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
   setNameFn(getResult(), getName());
 }
 
+//===----------------------------------------------------------------------===//
+// AssignedVarOp
+//===----------------------------------------------------------------------===//
+
+void AssignedVarOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
+  setNameFn(getResult(), getName());
+}
+
 //===----------------------------------------------------------------------===//
 // ConstantOp
 //===----------------------------------------------------------------------===//

test/Dialect/Moore/canonicalizers.mlir

@@ -9,3 +9,31 @@ func.func @Casts(%arg0: !moore.i1) -> (!moore.i1, !moore.i1) {
   // CHECK: return %arg0, %arg0
   return %0, %1 : !moore.i1, !moore.i1
 }
+
+// CHECK-LABEL: moore.module @SingleAssign
+moore.module @SingleAssign() {
+  // CHECK-NOT: moore.variable
+  // CHECK: %a = moore.assigned_variable %0 : <i32>
+  %a = moore.variable : <i32>
+  // CHECK: %0 = moore.constant 32 : i32
+  %0 = moore.constant 32 : i32
+  // CHECK: moore.assign %a, %0 : i32
+  moore.assign %a, %0 : i32
+  moore.output
+}
+
+// CHECK-LABEL: moore.module @MultiAssign
+moore.module @MultiAssign() {
+  // CHECK-NOT: moore.assigned_variable
+  // CHECK: %a = moore.variable : <i32>
+  %a = moore.variable : <i32>
+  // CHECK: %0 = moore.constant 32 : i32
+  %0 = moore.constant 32 : i32
+  // CHECK: moore.assign %a, %0 : i32
+  moore.assign %a, %0 : i32
+  // CHECK: %1 = moore.constant 64 : i32
+  %1 = moore.constant 64 : i32
+  // CHECK: moore.assign %a, %1 : i32
+  moore.assign %a, %1 : i32
+  moore.output
+}

tools/circt-verilog/circt-verilog.cpp

@@ -226,6 +226,7 @@ static LogicalResult populateMooreTransforms(mlir::PassManager &pm) {
 
   pm.addPass(mlir::createSROA());
   pm.addPass(mlir::createMem2Reg());
+
   // TODO: like dedup pass.
 
   return success();