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[Docs] fix typos in Dialects/ (#6555)
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shuoer86 authored Jan 7, 2024
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2 changes: 1 addition & 1 deletion docs/Dialects/ESI/cosim.md
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Expand Up @@ -76,7 +76,7 @@ module Cosim_Endpoint
```

The RPC interface allows clients to query all the registered endpoints, grab
a reference to one, and send/recieve messages and/or raw data. Once one
a reference to one, and send/receive messages and/or raw data. Once one
client opens an Endpoint, it is locked until said client closes it.

```capnp
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2 changes: 1 addition & 1 deletion docs/Dialects/ESI/types.md
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Expand Up @@ -38,7 +38,7 @@ rather, they speak to the signaling.
## Channels

ESI "channels" are streaming connections upon which *messages* can be sent and
recieved. They are expressed by wrapping the type (e.g. `!esi.channel<i5>`) and
received. They are expressed by wrapping the type (e.g. `!esi.channel<i5>`) and
using it like any other value type.

```mlir
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4 changes: 2 additions & 2 deletions docs/Dialects/FIRRTL/RationaleFIRRTL.md
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Expand Up @@ -761,7 +761,7 @@ operations related to Chisel memories are often referred to as CHIRRTL.
The main difference between Chisel and FIRRTL memories is that Chisel memories
have an operation to add a memory port to a memory, while FIRRTL memories
require all ports to be defined up front. Another difference is that Chisel
memories have "enable inferrence", and are usually inferred to be enabled where
memories have "enable inference", and are usually inferred to be enabled where
they are declared. The following example shows a CHIRRTL memory declaration, and
the standard FIRRTL memory equivalent.

Expand Down Expand Up @@ -1035,7 +1035,7 @@ to a constant zero.
## Intrinsics

Intrinsics are implementation-defined constructs. Intrinsics provide a way to
extend the system with funcitonality without changing the langauge. They form
extend the system with functionality without changing the language. They form
an implementation-specific built-in library. Unlike traditional libraries,
implementations of intrinsics have access to internals of the compiler, allowing
them to implement features not possible in the language.
2 changes: 1 addition & 1 deletion docs/Dialects/HW/RationaleHW.md
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Expand Up @@ -90,7 +90,7 @@ sequentially numbered in tag order from 0. Enum tags are unsigned values.
### `union` Type

Union types contain a single data element (which may be an aggregate). They
optionally have an offset per varient which allows non-SV layouts.
optionally have an offset per variant which allows non-SV layouts.

## `hw.module` and `hw.instance`

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2 changes: 1 addition & 1 deletion docs/Dialects/Pipeline/RationalePipeline.md
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Expand Up @@ -175,7 +175,7 @@ foo.bar %out_s4 : i32
**Note:** the following is only valid for pipelines with a stall signal.

An option of the Pipeline abstraction presented in this dialect is the ability
to have _non-stallable stages_ (NS). NS stages are used whereever a pipeline
to have _non-stallable stages_ (NS). NS stages are used wherever a pipeline
access resources that are not able to stop on a dime, and thus require a fixed
amount of cycles to complete.

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2 changes: 1 addition & 1 deletion docs/Dialects/SV/RationaleSV.md
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Expand Up @@ -145,7 +145,7 @@ Substitions also allow format specifier after a ':'. The meaning of said options
depends on the operand type or the operation pointed to by the symbol. So far,
the following format specifiers are supported:

- Symbol refering to a `hw.hierpath`: the separation string for joining names
- Symbol referring to a `hw.hierpath`: the separation string for joining names
in the path. Defaults to ".".

Example:
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2 changes: 1 addition & 1 deletion docs/Dialects/Seq/RationaleSeq.md
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Expand Up @@ -283,7 +283,7 @@ the structural details of a port into separate ops of which we currently
only provide rudimentary read- and write ops.
Example future ports could be:

* **Assymetric port widths**
* **Asymmetric port widths**
Specified as a new `seq.asym_read` port which defines a read data width
of some fraction of the native data size.
```mlir
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2 changes: 1 addition & 1 deletion docs/PyCDE/basics.md
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Expand Up @@ -71,7 +71,7 @@ Since CIRCT primarily targets hardware not software, it defines its own types.
PyCDE exposes them through the `pycde.types.Type` class hierarchy. PyCDE
signals represent values on the target device. Signals have a particular `Type`
(which is distinct from the signal objects' Python `type`) stored in their
`type` instance member. `Type`s are heretofor referred to interchangably as
`type` instance member. `Type`s are heretofor referred to interchangeably as
"PyCDE type", "CIRCT type", or "Type".

All signals extend the `pycde.signals.Signal` class, specialized by their Type.
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