Use getDiscardableAttr to access discardable attributes

llvm · Nov 1, 2024 · 38b49b1 · 38b49b1
1 parent f91b47e
commit 38b49b1
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Showing 2 changed files with 12 additions and 12 deletions.
diff --git a/lib/Conversion/FIRRTLToHW/LowerToHW.cpp b/lib/Conversion/FIRRTLToHW/LowerToHW.cpp
@@ -3015,11 +3015,11 @@ LogicalResult FIRRTLLowering::visitDecl(RegOp op) {
                                            op.getNameAttr(), innerSym);
 
   // Pass along the start and end random initialization bits for this register.
-  if (auto randomRegister = op->getAttr("firrtl.random_init_register"))
+  if (auto randomRegister = op->getDiscardableAttr("firrtl.random_init_register"))
     reg->setAttr("firrtl.random_init_register", randomRegister);
-  if (auto randomStart = op->getAttr("firrtl.random_init_start"))
+  if (auto randomStart = op->getDiscardableAttr("firrtl.random_init_start"))
     reg->setAttr("firrtl.random_init_start", randomStart);
-  if (auto randomEnd = op->getAttr("firrtl.random_init_end"))
+  if (auto randomEnd = op->getDiscardableAttr("firrtl.random_init_end"))
     reg->setAttr("firrtl.random_init_end", randomEnd);
 
   // Move SV attributes.
@@ -3056,11 +3056,11 @@ LogicalResult FIRRTLLowering::visitDecl(RegResetOp op) {
                                     resetSignal, resetValue, innerSym, isAsync);
 
   // Pass along the start and end random initialization bits for this register.
-  if (auto randomRegister = op->getAttr("firrtl.random_init_register"))
+  if (auto randomRegister = op->getDiscardableAttr("firrtl.random_init_register"))
     reg->setAttr("firrtl.random_init_register", randomRegister);
-  if (auto randomStart = op->getAttr("firrtl.random_init_start"))
+  if (auto randomStart = op->getDiscardableAttr("firrtl.random_init_start"))
     reg->setAttr("firrtl.random_init_start", randomStart);
-  if (auto randomEnd = op->getAttr("firrtl.random_init_end"))
+  if (auto randomEnd = op->getDiscardableAttr("firrtl.random_init_end"))
     reg->setAttr("firrtl.random_init_end", randomEnd);
 
   // Move SV attributes.
@@ -3296,7 +3296,7 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) {
                                              innerSym.getSymName());
     // If the lowered op already had output file information, then use that.
     // Otherwise, generate some default bind information.
-    if (auto outputFile = oldInstance->getAttr("output_file"))
+    if (auto outputFile = oldInstance->getDiscardableAttr("output_file"))
       bindOp->setAttr("output_file", outputFile);
     // Add the bind to the circuit state.  This will be moved outside of the
     // encapsulating module after all modules have been processed in parallel.

diff --git a/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp b/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp
@@ -545,7 +545,7 @@ static bool isAssertOp(hw::HWSymbolCache &symCache, Operation *op) {
   // phase and are not instances that could possibly have extract flags on them.
   if (auto inst = dyn_cast<hw::InstanceOp>(op))
     if (auto *mod = symCache.getDefinition(inst.getModuleNameAttr()))
-      if (mod->getAttr("firrtl.extract.assert.extra"))
+      if (mod->getDiscardableAttr("firrtl.extract.assert.extra"))
         return true;
 
   // If the format of assert is "ifElseFatal", PrintOp is lowered into
@@ -570,7 +570,7 @@ static bool isCoverOp(hw::HWSymbolCache &symCache, Operation *op) {
   // phase and are not instances that could possibly have extract flags on them.
   if (auto inst = dyn_cast<hw::InstanceOp>(op))
     if (auto *mod = symCache.getDefinition(inst.getModuleNameAttr()))
-      if (mod->getAttr("firrtl.extract.cover.extra"))
+      if (mod->getDiscardableAttr("firrtl.extract.cover.extra"))
         return true;
   return isa<CoverOp, CoverConcurrentOp, verif::CoverOp, verif::ClockedCoverOp>(
       op);
@@ -581,7 +581,7 @@ static bool isAssumeOp(hw::HWSymbolCache &symCache, Operation *op) {
   // phase and are not instances that could possibly have extract flags on them.
   if (auto inst = dyn_cast<hw::InstanceOp>(op))
     if (auto *mod = symCache.getDefinition(inst.getModuleNameAttr()))
-      if (mod->getAttr("firrtl.extract.assume.extra"))
+      if (mod->getDiscardableAttr("firrtl.extract.assume.extra"))
         return true;
 
   return isa<AssumeOp, AssumeConcurrentOp, verif::AssumeOp,
@@ -787,8 +787,8 @@ void SVExtractTestCodeImplPass::runOnOperation() {
         continue;
 
       // In the module is in test harness, we don't have to extract from it.
-      if (rtlmod->hasAttr("firrtl.extract.do_not_extract")) {
-        rtlmod->removeAttr("firrtl.extract.do_not_extract");
+      if (rtlmod->getDiscardableAttr("firrtl.extract.do_not_extract")) {
+        rtlmod->removeDiscardableAttr("firrtl.extract.do_not_extract");
         continue;
       }