Skip to content

Commit

Permalink
[SimToSV] Fix DPICall lowering to use replaceOp (#7192)
Browse files Browse the repository at this point in the history
Previously DPICallLowering called `rewriter.replaceAllUsesWith` for individual
results but it seems that is not equivalent to `replaceOp`. 

This also adds missing dialect dependency to seq

Close #7191
  • Loading branch information
uenoku authored Jun 17, 2024
1 parent 18d2872 commit 3e67926
Show file tree
Hide file tree
Showing 3 changed files with 18 additions and 4 deletions.
1 change: 1 addition & 0 deletions include/circt/Conversion/Passes.td
Original file line number Diff line number Diff line change
Expand Up @@ -808,6 +808,7 @@ def LowerSimToSV: Pass<"lower-sim-to-sv", "mlir::ModuleOp"> {
let dependentDialects = [
"circt::comb::CombDialect",
"circt::emit::EmitDialect",
"circt::seq::SeqDialect",
"circt::sv::SVDialect",
"circt::hw::HWDialect"
];
Expand Down
8 changes: 4 additions & 4 deletions lib/Conversion/SimToSV/SimToSV.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -180,12 +180,12 @@ class DPICallLowering : public SimConversionPattern<DPICallOp> {
bool hasEnable = !!op.getEnable();

SmallVector<sv::RegOp> temporaries;
SmallVector<Value> reads;
for (auto [type, result] :
llvm::zip(op.getResultTypes(), op.getResults())) {
temporaries.push_back(rewriter.create<sv::RegOp>(op.getLoc(), type));
auto read =
rewriter.create<sv::ReadInOutOp>(op.getLoc(), temporaries.back());
rewriter.replaceAllUsesWith(result, read);
reads.push_back(
rewriter.create<sv::ReadInOutOp>(op.getLoc(), temporaries.back()));
}

auto emitCall = [&]() {
Expand Down Expand Up @@ -229,7 +229,7 @@ class DPICallLowering : public SimConversionPattern<DPICallOp> {
});
}

rewriter.eraseOp(op);
rewriter.replaceOp(op, reads);
return success();
}
};
Expand Down
13 changes: 13 additions & 0 deletions test/Conversion/SimToSV/dpi.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -92,3 +92,16 @@ hw.module @dpi_call(in %clock : !seq.clock, in %enable : i1, in %in: i1,
// VERILOG-NEXT: assign o8 = [[RESULT_7]];
hw.output %0, %1, %2, %3, %4, %5, %6, %7: i1, i1, i1, i1, i1, i1, i1, i1
}

sim.func.dpi private @increment_counter(in %in_0 : i64, out out_0 : i32)
sim.func.dpi private @create_counter(out out_0 : i64)
// CHECK-LABEL: hw.module @Issue7191
// Check lowering successes.
hw.module @Issue7191(out result : i32) {
// CHECK: call.procedural @create_counter
// CHECK: call.procedural @increment_counter

%0 = sim.func.dpi.call @create_counter() : () -> i64
%1 = sim.func.dpi.call @increment_counter(%0) : (i64) -> i32
hw.output %1 : i32
}

0 comments on commit 3e67926

Please sign in to comment.