[LLHD] Fix misprint in llhd-desequentialize pass (#7985)

llvm · Dec 13, 2024 · 54d3dd0 · 54d3dd0
1 parent 6634b2b
commit 54d3dd0
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Showing 2 changed files with 25 additions and 1 deletion.
diff --git a/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp b/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp
@@ -472,7 +472,7 @@ class DnfAnalyzer {
                                OpBuilder &builder, Location loc) {
     for (auto *iter1 = triggers.begin(); iter1 != triggers.end(); ++iter1) {
       for (auto *iter2 = iter1 + 1; iter2 != triggers.end(); ++iter2) {
-        if (iter1->clocks == iter2->clocks && iter1->kinds == iter1->kinds) {
+        if (iter1->clocks == iter2->clocks && iter1->kinds == iter2->kinds) {
           iter1->enable =
               builder.create<comb::OrOp>(loc, iter1->enable, iter2->enable);
           triggers.erase(iter2--);

diff --git a/test/Dialect/LLHD/Transforms/desequentialization.mlir b/test/Dialect/LLHD/Transforms/desequentialization.mlir
@@ -135,3 +135,27 @@ hw.module @asyncResetNotObserved(inout %rst : i1, inout %clk : i1, inout %sig :
     cf.br ^bb1
   }
 }
+
+// CHECK-LABEL: @compareClkPrb
+// CHECK-SAME: (inout [[CLK:%.+]] : i1, inout [[OUT:%.+]] : i1)
+hw.module @compareClkPrb(inout %clk : i1, inout %out : i1) {
+  // CHECK: [[V0:%.+]] = llhd.prb [[CLK]]
+  // CHECK: [[V1:%.+]] = seq.to_clock [[V0]]
+  // CHECK: [[V2:%.+]] = comb.xor [[V0]], %true{{.*}}
+  // CHECK: [[V3:%.+]] = seq.compreg %false{{.*}}, [[V1]] reset [[V2]], %false{{.*}}
+  // CHECK: llhd.drv [[OUT]], [[V3]] after
+  %false = hw.constant false
+  %time = llhd.constant_time <0ns, 1d, 0e>
+  %clk_0 = llhd.prb %clk : !hw.inout<i1>
+  llhd.process {
+    cf.br ^bb1
+  ^bb1:
+    %clk_1 = llhd.prb %clk : !hw.inout<i1>
+    llhd.wait (%clk_0 : i1), ^bb2
+  ^bb2:
+    %clk_2 = llhd.prb %clk : !hw.inout<i1>
+    %cond = comb.icmp bin ne %clk_1, %clk_2 : i1
+    llhd.drv %out, %false after %time if %cond : !hw.inout<i1>
+    cf.br ^bb1
+  }
+}