[ImportVerilog] Support Generate constructs

llvm · Jun 28, 2024 · 72a6577 · 72a6577
1 parent 765cec6
commit 72a6577
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Showing 3 changed files with 67 additions and 1 deletion.
diff --git a/lib/Conversion/ImportVerilog/Structure.cpp b/lib/Conversion/ImportVerilog/Structure.cpp
@@ -98,6 +98,11 @@ struct MemberVisitor {
   LogicalResult visit(const slang::ast::PortSymbol &) { return success(); }
   LogicalResult visit(const slang::ast::MultiPortSymbol &) { return success(); }
 
+  // Skip genvars.
+  LogicalResult visit(const slang::ast::GenvarSymbol &genvarNode) {
+    return success();
+  }
+
   // Handle instances.
   LogicalResult visit(const slang::ast::InstanceSymbol &instNode) {
     using slang::ast::ArgumentDirection;
@@ -368,6 +373,26 @@ struct MemberVisitor {
     return success();
   }
 
+  // Handle generate block.
+  LogicalResult visit(const slang::ast::GenerateBlockSymbol &genNode) {
+    if (!genNode.isUninstantiated) {
+      for (auto &member : genNode.members()) {
+        if (failed(member.visit(MemberVisitor(context, loc))))
+          return failure();
+      }
+    }
+    return success();
+  }
+
+  // Handle generate block array.
+  LogicalResult visit(const slang::ast::GenerateBlockArraySymbol &genArrNode) {
+    for (const auto *member : genArrNode.entries) {
+      if (failed(member->asSymbol().visit(MemberVisitor(context, loc))))
+        return failure();
+    }
+    return success();
+  }
+
   // Ignore statement block symbols. These get generated by Slang for blocks
   // with variables and other declarations. For example, having an initial
   // procedure with a variable declaration, such as `initial begin int x;

diff --git a/test/Conversion/ImportVerilog/basic.sv b/test/Conversion/ImportVerilog/basic.sv
@@ -1258,3 +1258,43 @@ module EventControl(input clk);
   // CHECK: moore.assign %clk_0, %clk : l1
   // CHECK: moore.output
 endmodule
+
+// CHECK-LABEL: moore.module @GenerateConstructs()
+module GenerateConstructs;
+  genvar i;
+  parameter p=2;
+
+  generate
+    // CHECK: [[TMP1:%.+]] = moore.constant 0 : l32
+    // CHECK: %i = moore.named_constant localparam [[TMP1]] : l32
+    // CHECK: [[TMP2:%.+]] = moore.conversion %i : !moore.l32 -> !moore.i32
+    // CHECK: %g1 = moore.variable [[TMP2]] : <i32>
+    // CHECK: [[TMP3:%.+]] = moore.constant 1 : l32
+    // CHECK: %i_0 = moore.named_constant localparam name "i" [[TMP3]] : l32
+    // CHECK: [[TMP4:%.+]] = moore.conversion %i_0 : !moore.l32 -> !moore.i32
+    // CHECK: %g1_1 = moore.variable name "g1" [[TMP4]] : <i32>
+    for(i=0; i<2; i=i+1) begin
+      int g1 = i;
+    end
+
+    // CHECK: [[TMP:%.+]] = moore.constant 2 : i32
+    // CHECK: %g2 = moore.variable [[TMP]] : <i32>
+    if(p == 2) begin
+      int g2 = 2;
+    end
+    else begin
+      int g2 = 3;
+    end
+
+    // CHECK: [[TMP:%.+]] = moore.constant 2 : i32
+    // CHECK: %g3 = moore.variable [[TMP]] : <i32>
+    case (p)
+      2: begin
+        int g3 = 2;
+        end
+      default: begin
+        int g3 = 3;
+        end
+    endcase
+  endgenerate
+endmodule
diff --git a/test/Conversion/ImportVerilog/errors.sv b/test/Conversion/ImportVerilog/errors.sv
@@ -27,8 +27,9 @@ endmodule
 
 // -----
 module Foo;
+  parameter a = 1;
   // expected-error @below {{unsupported construct}}
-  genvar a;
+  defparam a = 2;
 endmodule
 
 // -----