[FIRRTL] Drop support for long-unused subcircuit annotations. (#6899)

This is a functional change in that these presently are ignored and will now be rejected.
llvm · Apr 5, 2024 · 7d96ea4 · 7d96ea4
1 parent 001c855
commit 7d96ea4
Show file tree

Hide file tree

Showing 5 changed files with 0 additions and 34 deletions.
diff --git a/docs/Dialects/FIRRTL/FIRRTLAnnotations.md b/docs/Dialects/FIRRTL/FIRRTLAnnotations.md
@@ -898,32 +898,6 @@ Example:
 }
 ```
 
-### SubCircuitsTargetDirectory
-
-| Property   | Type   | Description                                                        |
-| ---------- | ------ | -------------                                                      |
-| class      | string | `sifive.enterprise.grandcentral.phases.SubCircuitsTargetDirectory` |
-| dir        | string | The sub-circuit output directory                                   |
-
-This annotation is used to indicate the directory to serialize sub-circuits to
-by GrandCentral. Sub-circuits will be put in subdirectories of `dir`, named by
-their `circuitPackage` field.
-
-In the Scala FIRRTL compiler this is attached to the circuit with the
-commandline option `sub-circuits-target-dir`.
-```
--sub-circuit-targets-dir <dir>
--sctd <dir>
-```
-
-Example:
-```json
-{
-  "class":"sifive.enterprise.grandcentral.phases.SubCircuitsTargetDirectory",
-  "dir":"verilog/verif.subcircuits"
-}
-```
-
 ### TestBenchDirAnnotation
 
 | Property   | Type   | Description                                       |

diff --git a/include/circt/Dialect/FIRRTL/AnnotationDetails.h b/include/circt/Dialect/FIRRTL/AnnotationDetails.h
@@ -157,12 +157,8 @@ constexpr const char *scalaClassAnnoClass =
     "sifive.enterprise.firrtl.ScalaClassAnnotation";
 constexpr const char *elaborationArtefactsDirectoryAnnoClass =
     "sifive.enterprise.firrtl.ElaborationArtefactsDirectory";
-constexpr const char *subCircuitsTargetDirectoryAnnoClass =
-    "sifive.enterprise.grandcentral.phases.SubCircuitsTargetDirectory";
 constexpr const char *testHarnessPathAnnoClass =
     "sifive.enterprise.firrtl.TestHarnessPathAnnotation";
-constexpr const char *subCircuitDirAnnotation =
-    "sifive.enterprise.grandcentral.SubCircuitDirAnnotation";
 /// Annotation that marks a reset (port or wire) and domain.
 constexpr const char *fullAsyncResetAnnoClass =
     "sifive.enterprise.firrtl.FullAsyncResetAnnotation";

diff --git a/lib/Conversion/FIRRTLToHW/LowerToHW.cpp b/lib/Conversion/FIRRTLToHW/LowerToHW.cpp
@@ -521,7 +521,6 @@ void CircuitLoweringState::processRemainingAnnotations(
             // consuming these, they will linger around and can be ignored.
             scalaClassAnnoClass, dutAnnoClass, metadataDirectoryAttrName,
             elaborationArtefactsDirectoryAnnoClass, testBenchDirAnnoClass,
-            subCircuitsTargetDirectoryAnnoClass,
             // This annotation is used to mark which external modules are
             // imported blackboxes from the BlackBoxReader pass.
             blackBoxAnnoClass,

diff --git a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
@@ -475,7 +475,6 @@ static llvm::StringMap<AnnoRecord> annotationRecords{{
     {verifBlackBoxAnnoClass,
      {stdResolve, applyWithoutTarget<false, FExtModuleOp>}},
     {elaborationArtefactsDirectoryAnnoClass, NoTargetAnnotation},
-    {subCircuitsTargetDirectoryAnnoClass, NoTargetAnnotation},
     {retimeModulesFileAnnoClass, NoTargetAnnotation},
     {retimeModuleAnnoClass,
      {stdResolve, applyWithoutTarget<false, FModuleOp, FExtModuleOp>}},
@@ -486,7 +485,6 @@ static llvm::StringMap<AnnoRecord> annotationRecords{{
     {testHarnessHierAnnoClass, NoTargetAnnotation},
     {testHarnessPathAnnoClass, NoTargetAnnotation},
     {prefixInterfacesAnnoClass, NoTargetAnnotation},
-    {subCircuitDirAnnotation, NoTargetAnnotation},
     {extractAssertAnnoClass, NoTargetAnnotation},
     {extractAssumeAnnoClass, NoTargetAnnotation},
     {extractCoverageAnnoClass, NoTargetAnnotation},

diff --git a/test/Conversion/FIRRTLToHW/lower-to-hw-errors.mlir b/test/Conversion/FIRRTLToHW/lower-to-hw-errors.mlir
@@ -116,7 +116,6 @@ firrtl.circuit "Foo" attributes {annotations = [
     {class = "sifive.enterprise.firrtl.MetadataDirAnnotation", dirname = "metadata"},
     {class = "sifive.enterprise.firrtl.ElaborationArtefactsDirectory", dirname = "artefacts"},
     {class = "sifive.enterprise.firrtl.TestBenchDirAnnotation", dirname = "tb"},
-    {class = "sifive.enterprise.grandcentral.phases.SubCircuitsTargetDirectory", dir = "subcircuits"},
     {class = "sifive.enterprise.grandcentral.ExtractGrandCentralAnnotation", directory = "gct-dir", filename = "gct-dir/bindings.sv"}
   ]} {
     firrtl.module @Foo() attributes {annotations = [