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[DC CAPI][PyCDE] Add cmerge and demux handshake ops
- Adds cmerge and demux functions to the handshake pycde module. - Lowering them requires fixes to the conversion pass and the CAPI code.
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Original file line number | Diff line number | Diff line change |
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@@ -1,42 +1,50 @@ | ||
# RUN: %PYTHON% %s | FileCheck %s | ||
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from pycde import (Clock, Output, Input, generator, types, Module) | ||
from pycde.handshake import Func | ||
from pycde.handshake import Func, cmerge, demux | ||
from pycde.testing import unittestmodule | ||
from pycde.types import Bits, Channel | ||
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# CHECK: hw.module @Top(in %clk : !seq.clock, in %rst : i1, in %a : !esi.channel<i8>, out x : !esi.channel<i8>) | ||
# CHECK: [[R0:%.+]] = handshake.esi_instance @TestFunc "TestFunc" clk %clk rst %rst(%a) : (!esi.channel<i8>) -> !esi.channel<i8> | ||
# CHECK: hw.output [[R0]] : !esi.channel<i8> | ||
# CHECK: } | ||
# CHECK: handshake.func @TestFunc(%arg0: i8, ...) -> i8 | ||
# CHECK: hw.module @Top(in %clk : !seq.clock, in %rst : i1, in %a : !esi.channel<i8>, in %b : !esi.channel<i8>, out x : !esi.channel<i8>) | ||
# CHECK: %0:2 = handshake.esi_instance @TestFunc "TestFunc" clk %clk rst %rst(%a, %b) : (!esi.channel<i8>, !esi.channel<i8>) -> (!esi.channel<i8>, !esi.channel<i8>) | ||
# CHECK: hw.output %0#0 : !esi.channel<i8> | ||
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# CHECK: handshake.func @TestFunc(%arg0: i8, %arg1: i8, ...) -> (i8, i8) | ||
# CHECK: %result, %index = control_merge %arg0, %arg1 : i8, i1 | ||
# CHECK: %c15_i8 = hw.constant 15 : i8 | ||
# CHECK: %0 = comb.and bin %arg0, %c15_i8 : i8 | ||
# CHECK: return %0 : i8 | ||
# CHECK: } | ||
# CHECK: [[R0:%.+]] = comb.and bin %result, %c15_i8 : i8 | ||
# CHECK: %trueResult, %falseResult = cond_br %index, [[R0]] : i8 | ||
# CHECK: return %trueResult, %falseResult : i8, i8 | ||
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class TestFunc(Func): | ||
a = Input(Bits(8)) | ||
b = Input(Bits(8)) | ||
x = Output(Bits(8)) | ||
y = Output(Bits(8)) | ||
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@generator | ||
def build(ports): | ||
ports.x = ports.a & Bits(8)(0xF) | ||
c, sel = cmerge(ports.a, ports.b) | ||
z = c & Bits(8)(0xF) | ||
x, y = demux(sel, z) | ||
ports.x = x | ||
ports.y = y | ||
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BarType = types.struct({"foo": types.i12}, "bar") | ||
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@unittestmodule(print=True, run_passes=True) | ||
@unittestmodule(print=True) | ||
class Top(Module): | ||
clk = Clock() | ||
rst = Input(Bits(1)) | ||
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a = Input(Channel(Bits(8))) | ||
b = Input(Channel(Bits(8))) | ||
x = Output(Channel(Bits(8))) | ||
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@generator | ||
def build(ports): | ||
test = TestFunc(clk=ports.clk, rst=ports.rst, a=ports.a) | ||
test = TestFunc(clk=ports.clk, rst=ports.rst, a=ports.a, b=ports.b) | ||
ports.x = test.x |
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