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buildLibraryOp cast floating point to integer types
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@jiahanxie353
jiahanxie353 committed Dec 12, 2024
1 parent bac37a3 commit e67b3c2
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14 changes: 12 additions & 2 deletions lib/Conversion/SCFToCalyx/SCFToCalyx.cpp
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Expand Up @@ -396,9 +396,19 @@ class BuildOpGroups : public calyx::FuncOpPartialLoweringPattern {
template <typename TGroupOp, typename TCalyxLibOp, typename TSrcOp>
LogicalResult buildLibraryOp(PatternRewriter &rewriter, TSrcOp op,
TypeRange srcTypes, TypeRange dstTypes) const {
auto castToInteger = [](Type type) -> Type {
if (isa<FloatType>(type)) {
unsigned bitWidth = cast<FloatType>(type).getWidth();
return IntegerType::get(type.getContext(), bitWidth);
}
return type;
};

SmallVector<Type> types;
llvm::append_range(types, srcTypes);
llvm::append_range(types, dstTypes);
for (Type srcType : srcTypes)
types.push_back(castToInteger(srcType));
for (Type dstType : dstTypes)
types.push_back(castToInteger(dstType));

auto calyxOp =
getState<ComponentLoweringState>().getNewLibraryOpInstance<TCalyxLibOp>(
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69 changes: 69 additions & 0 deletions test/Conversion/SCFToCalyx/convert_simple.mlir
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Expand Up @@ -438,3 +438,72 @@ module {
}
}

// -----

// Test lowering SelectOp with floating point operands

// CHECK: %std_mux_1.cond, %std_mux_1.tru, %std_mux_1.fal, %std_mux_1.out = calyx.std_mux @std_mux_1 : i1, i64, i64, i64
// CHECK-DAG: %unordered_port_1_reg.in, %unordered_port_1_reg.write_en, %unordered_port_1_reg.clk, %unordered_port_1_reg.reset, %unordered_port_1_reg.out, %unordered_port_1_reg.done = calyx.register @unordered_port_1_reg : i1, i1, i1, i1, i1, i1
// CHECK-DAG: %cmpf_1_reg.in, %cmpf_1_reg.write_en, %cmpf_1_reg.clk, %cmpf_1_reg.reset, %cmpf_1_reg.out, %cmpf_1_reg.done = calyx.register @cmpf_1_reg : i1, i1, i1, i1, i1, i1
// CHECK-DAG: %std_compareFN_1.clk, %std_compareFN_1.reset, %std_compareFN_1.go, %std_compareFN_1.left, %std_compareFN_1.right, %std_compareFN_1.signaling, %std_compareFN_1.lt, %std_compareFN_1.eq, %std_compareFN_1.gt, %std_compareFN_1.unordered, %std_compareFN_1.exceptionalFlags, %std_compareFN_1.done = calyx.ieee754.compare @std_compareFN_1 : i1, i1, i1, i64, i64, i1, i1, i1, i1, i1, i5, i1
// CHECK-DAG: %std_mux_0.cond, %std_mux_0.tru, %std_mux_0.fal, %std_mux_0.out = calyx.std_mux @std_mux_0 : i1, i64, i64, i64
// CHECK-DAG: %std_and_0.left, %std_and_0.right, %std_and_0.out = calyx.std_and @std_and_0 : i1, i1, i1
// CHECK-DAG: %std_or_0.left, %std_or_0.right, %std_or_0.out = calyx.std_or @std_or_0 : i1, i1, i1
// CHECK-DAG: %unordered_port_0_reg.in, %unordered_port_0_reg.write_en, %unordered_port_0_reg.clk, %unordered_port_0_reg.reset, %unordered_port_0_reg.out, %unordered_port_0_reg.done = calyx.register @unordered_port_0_reg : i1, i1, i1, i1, i1, i1
// CHECK-DAG: %compare_port_0_reg.in, %compare_port_0_reg.write_en, %compare_port_0_reg.clk, %compare_port_0_reg.reset, %compare_port_0_reg.out, %compare_port_0_reg.done = calyx.register @compare_port_0_reg : i1, i1, i1, i1, i1, i1
// CHECK-DAG: %cmpf_0_reg.in, %cmpf_0_reg.write_en, %cmpf_0_reg.clk, %cmpf_0_reg.reset, %cmpf_0_reg.out, %cmpf_0_reg.done = calyx.register @cmpf_0_reg : i1, i1, i1, i1, i1, i1
// CHECK-DAG: %std_compareFN_0.clk, %std_compareFN_0.reset, %std_compareFN_0.go, %std_compareFN_0.left, %std_compareFN_0.right, %std_compareFN_0.signaling, %std_compareFN_0.lt, %std_compareFN_0.eq, %std_compareFN_0.gt, %std_compareFN_0.unordered, %std_compareFN_0.exceptionalFlags, %std_compareFN_0.done = calyx.ieee754.compare @std_compareFN_0 : i1, i1, i1, i64, i64, i1, i1, i1, i1, i1, i5, i1
// CHECK: calyx.wires {
// CHECK: calyx.group @bb0_0 {
// CHECK-DAG: calyx.assign %std_compareFN_0.left = %in0 : i64
// CHECK-DAG: calyx.assign %std_compareFN_0.right = %in1 : i64
// CHECK-DAG: calyx.assign %std_compareFN_0.signaling = %true : i1
// CHECK-DAG: calyx.assign %compare_port_0_reg.write_en = %std_compareFN_0.done : i1
// CHECK-DAG: calyx.assign %compare_port_0_reg.in = %std_compareFN_0.gt : i1
// CHECK-DAG: calyx.assign %unordered_port_0_reg.write_en = %std_compareFN_0.done : i1
// CHECK-DAG: calyx.assign %unordered_port_0_reg.in = %std_compareFN_0.unordered : i1
// CHECK-DAG: calyx.assign %std_or_0.left = %compare_port_0_reg.out : i1
// CHECK-DAG: calyx.assign %std_or_0.right = %unordered_port_0_reg.out : i1
// CHECK-DAG: calyx.assign %std_and_0.left = %compare_port_0_reg.done : i1
// CHECK-DAG: calyx.assign %std_and_0.right = %unordered_port_0_reg.done : i1
// CHECK-DAG: calyx.assign %cmpf_0_reg.in = %std_or_0.out : i1
// CHECK-DAG: calyx.assign %cmpf_0_reg.write_en = %std_and_0.out : i1
// CHECK-DAG: %0 = comb.xor %std_compareFN_0.done, %true : i1
// CHECK-DAG: calyx.assign %std_compareFN_0.go = %0 ? %true : i1
// CHECK-DAG: calyx.group_done %cmpf_0_reg.done : i1
// CHECK-DAG: }
// CHECK: calyx.group @bb0_2 {
// CHECK-DAG: calyx.assign %std_compareFN_1.left = %in1 : i64
// CHECK-DAG: calyx.assign %std_compareFN_1.right = %in1 : i64
// CHECK-DAG: calyx.assign %std_compareFN_1.signaling = %false : i1
// CHECK-DAG: calyx.assign %unordered_port_1_reg.write_en = %std_compareFN_1.done : i1
// CHECK-DAG: calyx.assign %unordered_port_1_reg.in = %std_compareFN_1.unordered : i1
// CHECK-DAG: calyx.assign %cmpf_1_reg.in = %unordered_port_1_reg.out : i1
// CHECK-DAG: calyx.assign %cmpf_1_reg.write_en = %unordered_port_1_reg.out : i1
// CHECK-DAG: %0 = comb.xor %std_compareFN_1.done, %true : i1
// CHECK-DAG: calyx.assign %std_compareFN_1.go = %0 ? %true : i1
// CHECK-DAG: calyx.group_done %cmpf_1_reg.done : i1
// CHECK-DAG: }
// CHECK: calyx.group @ret_assign_0 {
// CHECK-DAG: calyx.assign %ret_arg0_reg.in = %std_mux_1.out : i64
// CHECK-DAG: calyx.assign %ret_arg0_reg.write_en = %true : i1
// CHECK-DAG: calyx.assign %std_mux_1.cond = %cmpf_1_reg.out : i1
// CHECK-DAG: calyx.assign %std_mux_1.tru = %in1 : i64
// CHECK-DAG: calyx.assign %std_mux_1.fal = %std_mux_0.out : i64
// CHECK-DAG: calyx.assign %std_mux_0.cond = %cmpf_0_reg.out : i1
// CHECK-DAG: calyx.assign %std_mux_0.tru = %in0 : i64
// CHECK-DAG: calyx.assign %std_mux_0.fal = %in1 : i64
// CHECK-DAG: calyx.group_done %ret_arg0_reg.done : i1
// CHECK-DAG: }
// CHECK-DAG: }

module {
func.func @main(%arg0: f64, %arg1: f64) -> f64 {
%0 = arith.cmpf ugt, %arg0, %arg1 : f64
%1 = arith.select %0, %arg0, %arg1 : f64
%2 = arith.cmpf uno, %arg1, %arg1 : f64
%3 = arith.select %2, %arg1, %1 : f64
return %3 : f64
}
}

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