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[ImportVerilog] Support Generate constructs #7243

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25 changes: 25 additions & 0 deletions lib/Conversion/ImportVerilog/Structure.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -98,6 +98,11 @@ struct MemberVisitor {
LogicalResult visit(const slang::ast::PortSymbol &) { return success(); }
LogicalResult visit(const slang::ast::MultiPortSymbol &) { return success(); }

// Skip genvars.
LogicalResult visit(const slang::ast::GenvarSymbol &genvarNode) {
return success();
}

// Handle instances.
LogicalResult visit(const slang::ast::InstanceSymbol &instNode) {
using slang::ast::ArgumentDirection;
Expand Down Expand Up @@ -368,6 +373,26 @@ struct MemberVisitor {
return success();
}

// Handle generate block.
LogicalResult visit(const slang::ast::GenerateBlockSymbol &genNode) {
if (!genNode.isUninstantiated) {
for (auto &member : genNode.members()) {
if (failed(member.visit(MemberVisitor(context, loc))))
return failure();
}
}
return success();
}

// Handle generate block array.
LogicalResult visit(const slang::ast::GenerateBlockArraySymbol &genArrNode) {
for (const auto *member : genArrNode.entries) {
if (failed(member->asSymbol().visit(MemberVisitor(context, loc))))
return failure();
}
Comment on lines +389 to +392
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Oh interesting. Does Slang resolve generate statements in their side?

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Yes! Slang will expand all structures as GenerateBlock, here is the JSON of two GenerateBlocks, we can figure out which will be generated by isUninstantiated:

{
  "name": "",
  "kind": "GenerateBlock",
  "addr": 110809374896152,
  "members": [
    {
      "name": "g3",
      "kind": "Variable",
      "addr": 110809374896280,
      "type": "int",
      "initializer": {
        "kind": "IntegerLiteral",
        "type": "int",
        "value": "2",
        "constant": "2"
      },
      "lifetime": "Static"
    }
  ],
  "constructIndex": 3,
  "isUninstantiated": false
},
{
  "name": "",
  "kind": "GenerateBlock",
  "addr": 110809374896624,
  "members": [
    {
      "name": "g3",
      "kind": "Variable",
      "addr": 110809374896752,
      "type": "int",
      "initializer": {
        "kind": "IntegerLiteral",
        "type": "int",
        "value": "3",
        "constant": "3"
      },
      "lifetime": "Static"
    }
  ],
  "constructIndex": 3,
  "isUninstantiated": true
}

return success();
}

// Ignore statement block symbols. These get generated by Slang for blocks
// with variables and other declarations. For example, having an initial
// procedure with a variable declaration, such as `initial begin int x;
Expand Down
40 changes: 40 additions & 0 deletions test/Conversion/ImportVerilog/basic.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1258,3 +1258,43 @@ module EventControl(input clk);
// CHECK: moore.assign %clk_0, %clk : l1
// CHECK: moore.output
endmodule

// CHECK-LABEL: moore.module @GenerateConstructs()
module GenerateConstructs;
genvar i;
parameter p=2;

generate
// CHECK: [[TMP1:%.+]] = moore.constant 0 : l32
// CHECK: %i = moore.named_constant localparam [[TMP1]] : l32
// CHECK: [[TMP2:%.+]] = moore.conversion %i : !moore.l32 -> !moore.i32
// CHECK: %g1 = moore.variable [[TMP2]] : <i32>
// CHECK: [[TMP3:%.+]] = moore.constant 1 : l32
// CHECK: %i_0 = moore.named_constant localparam name "i" [[TMP3]] : l32
// CHECK: [[TMP4:%.+]] = moore.conversion %i_0 : !moore.l32 -> !moore.i32
// CHECK: %g1_1 = moore.variable name "g1" [[TMP4]] : <i32>
for(i=0; i<2; i=i+1) begin
int g1 = i;
end

// CHECK: [[TMP:%.+]] = moore.constant 2 : i32
// CHECK: %g2 = moore.variable [[TMP]] : <i32>
if(p == 2) begin
int g2 = 2;
end
else begin
int g2 = 3;
end

// CHECK: [[TMP:%.+]] = moore.constant 2 : i32
// CHECK: %g3 = moore.variable [[TMP]] : <i32>
case (p)
2: begin
int g3 = 2;
end
default: begin
int g3 = 3;
end
endcase
endgenerate
endmodule
3 changes: 2 additions & 1 deletion test/Conversion/ImportVerilog/errors.sv
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,9 @@ endmodule

// -----
module Foo;
parameter a = 1;
// expected-error @below {{unsupported construct}}
genvar a;
defparam a = 2;
endmodule

// -----
Expand Down
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