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[ImportVerilog]Dedup module Op #7245

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merged 26 commits into from
Jul 18, 2024
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mingzheTerapines
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@mingzheTerapines mingzheTerapines commented Jun 27, 2024

Dedup module Op while instance generating.

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@fabianschuiki @hailongSun2000 Sorry, last dedup PR was ruined after git rebase, please have a look at this one, thanks.

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Very cool! Minor comment regarding the nested test, but besides that this is very nice!

test/Conversion/ImportVerilog/basic.sv Outdated Show resolved Hide resolved
@hailongSun2000 hailongSun2000 merged commit d3ce6f6 into llvm:main Jul 18, 2024
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@mingzheTerapines mingzheTerapines deleted the mingzhe-DedupOpt branch July 18, 2024 02:29
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3 participants