Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[FIRRTL] Fix use-after-free in InferReset #7273

Merged
merged 2 commits into from
Jul 3, 2024
Merged

[FIRRTL] Fix use-after-free in InferReset #7273

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
ad0a34c
[FIRRTL] Fix use-after-free in InferReset
darthscsi Jul 2, 2024
dd6659e
fix tests
darthscsi Jul 2, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 11 additions & 3 deletions lib/Dialect/FIRRTL/Transforms/InferResets.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1714,14 +1714,22 @@ LogicalResult InferResetsPass::implementAsyncReset(FModuleOp module,
if (nodeOp && !dom.dominates(nodeOp.getInput(), opsToUpdate[0])) {
LLVM_DEBUG(llvm::dbgs()
<< "- Promoting node to wire for move: " << nodeOp << "\n");
ImplicitLocOpBuilder builder(nodeOp.getLoc(), nodeOp);
auto builder = ImplicitLocOpBuilder::atBlockBegin(nodeOp.getLoc(),
nodeOp->getBlock());
auto wireOp = builder.create<WireOp>(
nodeOp.getResult().getType(), nodeOp.getNameAttr(),
nodeOp.getNameKindAttr(), nodeOp.getAnnotationsAttr(),
nodeOp.getInnerSymAttr(), nodeOp.getForceableAttr());
emitConnect(builder, wireOp.getResult(), nodeOp.getInput());
// Don't delete the node, since it might be in use in worklists.
nodeOp->replaceAllUsesWith(wireOp);
nodeOp.erase();
nodeOp->removeAttr(nodeOp.getInnerSymAttrName());
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Should probably remove the annotations as well, e.g. if the node has an OMIR path tracker we will end up having two things with the same path tracker.

Not as important but might want to make the Node non-forcible.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

yea working on it.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Changing the node to be non-forcable is kind of a pain as it would requiring changing the number of results, which I don't think you can do. The forcable result should be unused, so it should be cleared away with the rest of the node by CSE/Canonicalization.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yes you can't change results, the way it's done is a bit rough but basically creates a new one and replaces it.

And even if you did that (there's a helper, but in the detail namespace) it'd be erasing the existing node so no-go.

Thanks!!

nodeOp.setName("");
// Leave forcable alone, since we cannot remove a result. It will be
// cleaned up in canonicalization since it is dead. As will this node.
nodeOp.setNameKind(NameKindEnum::DroppableName);
nodeOp.setAnnotationsAttr(ArrayAttr::get(builder.getContext(), {}));
builder.setInsertionPointAfter(nodeOp);
emitConnect(builder, wireOp.getResult(), nodeOp.getResult());
resetOp = wireOp;
actualReset = wireOp.getResult();
domain.existingValue = wireOp.getResult();
Expand Down
36 changes: 30 additions & 6 deletions test/Dialect/FIRRTL/infer-resets.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -625,7 +625,8 @@ firrtl.circuit "UnmovableNodeShouldDominate" {
// CHECK-NEXT: [[RV:%.+]] = firrtl.constant 0
// CHECK-NEXT: %reg = firrtl.regreset %clock, %localReset, [[RV]]
// CHECK-NEXT: %0 = firrtl.asAsyncReset %ui1
// CHECK-NEXT: firrtl.matchingconnect %localReset, %0
// CHECK-NEXT: %1 = firrtl.node %0 :
// CHECK-NEXT: firrtl.matchingconnect %localReset, %1 :
}
}

Expand All @@ -642,7 +643,8 @@ firrtl.circuit "UnmovableForceableNodeShouldDominate" {
// CHECK-NEXT: [[RV:%.+]] = firrtl.constant 0
// CHECK-NEXT: %reg = firrtl.regreset %clock, %localReset, [[RV]]
// CHECK-NEXT: %0 = firrtl.asAsyncReset %ui1
// CHECK-NEXT: firrtl.matchingconnect %localReset, %0
// CHECK-NEXT: %1:2 = firrtl.node %0 forceable
// CHECK-NEXT: firrtl.matchingconnect %localReset, %1#0
}
}

Expand All @@ -667,7 +669,8 @@ firrtl.circuit "MoveAcrossBlocks1" {
// CHECK-NEXT: }
// CHECK-NEXT: firrtl.when %ui1 : !firrtl.uint<1> {
// CHECK-NEXT: [[TMP:%.+]] = firrtl.asAsyncReset %ui1
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP]]
// CHECK-NEXT: [[TMP2:%.+]] = firrtl.node [[TMP]] : !firrtl.asyncreset
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP2]]
// CHECK-NEXT: }
}
}
Expand All @@ -688,7 +691,8 @@ firrtl.circuit "MoveAcrossBlocks2" {
// CHECK-NEXT: %localReset = firrtl.wire
// CHECK-NEXT: firrtl.when %ui1 : !firrtl.uint<1> {
// CHECK-NEXT: [[TMP:%.+]] = firrtl.asAsyncReset %ui1
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP]]
// CHECK-NEXT: [[TMP2:%.+]] = firrtl.node [[TMP]] : !firrtl.asyncreset
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP2]]
// CHECK-NEXT: }
// CHECK-NEXT: firrtl.when %ui1 : !firrtl.uint<1> {
// CHECK-NEXT: [[RV:%.+]] = firrtl.constant 0
Expand All @@ -713,7 +717,8 @@ firrtl.circuit "MoveAcrossBlocks3" {
// CHECK-NEXT: %reg = firrtl.regreset %clock, %localReset, [[RV]]
// CHECK-NEXT: firrtl.when %ui1 : !firrtl.uint<1> {
// CHECK-NEXT: [[TMP:%.+]] = firrtl.asAsyncReset %ui1
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP]]
// CHECK-NEXT: [[TMP2:%.+]] = firrtl.node [[TMP]] : !firrtl.asyncreset
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP2]]
// CHECK-NEXT: }
}
}
Expand All @@ -735,7 +740,8 @@ firrtl.circuit "MoveAcrossBlocks4" {
// CHECK-NEXT: %reg = firrtl.regreset %clock, %localReset, [[RV]]
// CHECK-NEXT: }
// CHECK-NEXT: [[TMP:%.+]] = firrtl.asAsyncReset %ui1
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP]]
// CHECK-NEXT: [[TMP2:%.+]] = firrtl.node [[TMP]] : !firrtl.asyncreset
// CHECK-NEXT: firrtl.matchingconnect %localReset, [[TMP2]]
}
}

Expand Down Expand Up @@ -1128,3 +1134,21 @@ firrtl.circuit "RWProbeOp" {
}
}

// -----

// CHECK-LABEL: "MovableNodeShouldDominateInstance"
firrtl.circuit "MovableNodeShouldDominateInstance" {
firrtl.module @MovableNodeShouldDominateInstance(in %clock: !firrtl.clock) {
%child_clock = firrtl.instance child @Child(in clock: !firrtl.clock)
firrtl.connect %child_clock, %clock : !firrtl.clock
%ui1 = firrtl.constant 1 : !firrtl.uint<1>
%0 = firrtl.asAsyncReset %ui1 : (!firrtl.uint<1>) -> !firrtl.asyncreset
%localReset = firrtl.node %0 {annotations = [{class = "sifive.enterprise.firrtl.FullAsyncResetAnnotation"}]} : !firrtl.asyncreset
// CHECK: %localReset = firrtl.wire {annotations = [{class = "sifive.enterprise.firrtl.FullAsyncResetAnnotation"}]} : !firrtl.asyncreset
// CHECK: %child_localReset, %child_clock = firrtl.instance child @Child(in localReset: !firrtl.asyncreset, in clock: !firrtl.clock
}
firrtl.module @Child(in %clock: !firrtl.clock) {
// CHECK: firrtl.regreset %clock, %localReset, %c0_ui8
%reg = firrtl.reg %clock : !firrtl.clock, !firrtl.uint<8>
}
}
Loading