[RTGTest] Add some registers #7924
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fabianschuiki
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Dec 4, 2024
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| Virtual registers will be assigned a concrete register when running register | ||
| allocation. |
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This probably doesn't make sense for a test dialect, but in practice, would you have virtual registers as a separate op that cannot be CSEd, and actual ISA register as something "pure" or maybe even "constant-like"?
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Good point! Having concrete registers CSE would be very nice. Having separate ops for concrete and virtual registers complicates register allocation a bit but makes elaboration easier. Let me think about that a bit more.
maerhart
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Dec 5, 2024
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| // Flat allocation of unique IDs to all registers. The actual ID value does not | ||
| // matter. | ||
| def RegisterAttr : I32EnumAttr< |
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I think ideally this attribute should be of IntegerRegisterType, not I32. It's not a big deal for now though.
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This adds some registers to later test passes such as register alloction, assembly emission, correct behavior of the elaboration pass in presence of registers, etc. Co-authored-by: Andrew Lenharth <[email protected]>
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This adds some registers to later test passes such as register alloction, assembly emission, correct behavior of the elaboration pass in presence of registers, etc.