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[LLHD] Fix misprint in llhd-desequentialize pass #7985

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merged 1 commit into from
Dec 13, 2024
Merged

[LLHD] Fix misprint in llhd-desequentialize pass #7985

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2 changes: 1 addition & 1 deletion lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -472,7 +472,7 @@ class DnfAnalyzer {
OpBuilder &builder, Location loc) {
for (auto *iter1 = triggers.begin(); iter1 != triggers.end(); ++iter1) {
for (auto *iter2 = iter1 + 1; iter2 != triggers.end(); ++iter2) {
if (iter1->clocks == iter2->clocks && iter1->kinds == iter1->kinds) {
if (iter1->clocks == iter2->clocks && iter1->kinds == iter2->kinds) {
iter1->enable =
builder.create<comb::OrOp>(loc, iter1->enable, iter2->enable);
triggers.erase(iter2--);
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24 changes: 24 additions & 0 deletions test/Dialect/LLHD/Transforms/desequentialization.mlir
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Expand Up @@ -135,3 +135,27 @@ hw.module @asyncResetNotObserved(inout %rst : i1, inout %clk : i1, inout %sig :
cf.br ^bb1
}
}

// CHECK-LABEL: @compareClkPrb
// CHECK-SAME: (inout [[CLK:%.+]] : i1, inout [[OUT:%.+]] : i1)
hw.module @compareClkPrb(inout %clk : i1, inout %out : i1) {
// CHECK: [[V0:%.+]] = llhd.prb [[CLK]]
// CHECK: [[V1:%.+]] = seq.to_clock [[V0]]
// CHECK: [[V2:%.+]] = comb.xor [[V0]], %true{{.*}}
// CHECK: [[V3:%.+]] = seq.compreg %false{{.*}}, [[V1]] reset [[V2]], %false{{.*}}
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Note: this is currently incorrect as it should be an async reset, but seq.compreg does not support that (we need a register in the seq dialect that supports that without having the FIRRTL specific parts of firreg).
No need to change anything in this PR.

// CHECK: llhd.drv [[OUT]], [[V3]] after
%false = hw.constant false
%time = llhd.constant_time <0ns, 1d, 0e>
%clk_0 = llhd.prb %clk : !hw.inout<i1>
llhd.process {
cf.br ^bb1
^bb1:
%clk_1 = llhd.prb %clk : !hw.inout<i1>
llhd.wait (%clk_0 : i1), ^bb2
^bb2:
%clk_2 = llhd.prb %clk : !hw.inout<i1>
%cond = comb.icmp bin ne %clk_1, %clk_2 : i1
llhd.drv %out, %false after %time if %cond : !hw.inout<i1>
cf.br ^bb1
}
}
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