Firtool Release 1.76.0

What's Changed

• [FIRRTL][NFC] Replace intmodules with intrinsic expressions in test. by @dtzSiFive in #7041
• [Arc] Add SplitFuncsPass by @TaoBi22 in #7027
• [Moore] Move IntType definition into ODS by @fabianschuiki in #7035
• [FIRRTL][Intrinsics] source materialization for inferred types. by @dtzSiFive in #7043
• [ESI][Cosim][NFC] Refactor cosim to divorce capnp from DPI by @teqdruid in #7045
• [SV] Add sv.func, sv.return and sv.func.call operations by @uenoku in #7003
• [SV] Add DPI import op by @uenoku in #7005
• [CreateSifiveMetadata] Fix a typo in the field name by @prithayan in #7046
• [SV][Folds] Fix ForOp canonicalizer to use rewriter. by @dtzSiFive in #7048
• [HW] Fix pattern returning success() without changing. by @dtzSiFive in #7053
• [Comb] Fix MuxRewriter to eraseOperand in rewriter-aware way. by @dtzSiFive in #7054
• [LLHD] Fix operand assignments not going through rewriter. by @dtzSiFive in #7055
• FileCheck directive fixup, now filecheck_lint-clean. by @dtzSiFive in #7057
• [Moore] Simplify and move RealType definition into ODS by @fabianschuiki in #7036
• [ESI][Runtime] Refactor cosim backend to be thread safe by @teqdruid in #7059
• [FIRRTL] Fix width of attribute in MuxPadSel canonicalizations. by @dtzSiFive in #7056
• [FIRRTL,PASS] Simple module summary looking for likely to dedup larger or numerous modules. This is to guide developers in using chisel better. by @darthscsi in #6935
• [FIRRTL][Import] Remove support for printf-encoded verif. by @dtzSiFive in #7030
• [FIRRTL][Folds] Fix patterns to use rewriter for RAUW by @dtzSiFive in #7049
• [LTL] Add repeat and until operators by @liuyic00 in #6989
• [FIRRTL] Reject intrinsic modules >= 4.0.0 by @dtzSiFive in #7009
• [PyCDE] Move build and publishing pipeline into repo by @teqdruid in #7062
• [FIRRTL][LowerClasses] Improve performance, NFC by @uenoku in #7060
• [FIRRTL] Convert Wires into Nodes by @darthscsi in #7067
• [FIRRTL] Register reset elimination based on invalid can look through nodes. by @darthscsi in #7069
• [FIRRTL] Remove unused and expensive API, NFC by @uenoku in #7076
• [FIRRTL] Preserve all analysis if nothing happens by @uenoku in #7077
• [FIRRTL] Limited invalid propagation. by @darthscsi in #7074
• LLVM bump by @youngar in #7079
• [ImportVerilog] Support member-access expression by @mingzheTerapines in #7039
• [ImportVerilog] Support set membership operator. by @angelzzzzz in #7066
• [LowerClasses] Ensure classes are instantiated by an object. by @prithayan in #7072
• [Verif] Add clocked Assert Assume Cover ops by @dobios in #7022
• [LTL] Add ops that allow for most of SVA to be modeled with LTL by @dobios in #7065
• [Seq] Fix incorrect folder by @uenoku in #7085
• [Arc] Modify VectorizeOp to support AnyType by @elhewaty in #7087
• [Moore] Move array types into ODS by @fabianschuiki in #7088
• [Moore] Support stripped type parsing and printing by @fabianschuiki in #7090
• [Moore] Move struct types into ODS by @fabianschuiki in #7091
• [Arc] Initial SLP support by @elhewaty in #7061
• [SMT] Added support for :pattern attribute by @luisacicolini in #6976
• [FIRRTL] Drop Hoistpassthroughs pass. by @dtzSiFive in #7097
• [CombToSMT] Register dependency on func by @maerhart in #7098
• [firtool] Add an option to export SV without SVA by @dobios in #7081
• [Arc] Fix crashes in FindInitialVectors Pass by @elhewaty in #7100
• [ImportVerilog][Moore] Support union type by @mingzheTerapines in #7084
• [FIRRTL][LowerClass] Pre-allocate namespaces before capturing references by @uenoku in #7102
• LLVM bump by @debs-sifive in #7103
• [ImportVerilog] Support parameter constants. by @angelzzzzz in #7083
• [FIRRTL] Visitor: Add missing ops, fix GenericIntrinsicOp visit. by @dtzSiFive in #7107
• [FIRRTL] Generate memportaccess op index as UInt. by @dtzSiFive in #7108
• CMake: Fix CIRCT_ENABLE_FRONTENDS to be string not bool. by @dtzSiFive in #7110
• [Arc] Add statistics to the FindInitialVectors pass by @elhewaty in #7113
• [NFC, FIRRTL] Rename StrictConnect to MatchingConnect. by @darthscsi in #7116
• [FIRRTL] Simplify path handling in ResolvePaths and LowerClasses. by @mikeurbach in #7129
• [FIRRTL] Actually copy the leading part of the path in LowerClasses. by @mikeurbach in #7130
• [Moore] Add module and instance port support by @fabianschuiki in #7112
• [FIRRTL][DropConst] Fix performance with many extmodule's. by @dtzSiFive in #7126
• [ImportVerilog] Add conditional operator. by @angelzzzzz in #6950

New Contributors

• @liuyic00 made their first contribution in #6989
• @mingzheTerapines made their first contribution in #7039
• @elhewaty made their first contribution in #7087

Full Changelog: firtool-1.75.0...firtool-1.76.0