firtool-1.96.0

What's Changed

• [VerifToSMT] Only update registers on clock posedge by @TaoBi22 in #7878
• [Verif] Require a clock when num_regs is non-zero on a BMC op by @TaoBi22 in #7891
• [Ibis] Rename to 'Kanagawa' by @teqdruid in #7832
• [firtool] Run LowerFormalToHW pass when emitting SV by @fabianschuiki in #7837
• [firtool] Fix formal test by @fabianschuiki in #7894
• SCF IndexSwitch to nested If-Else by @jiahanxie353 in #7670
• [CI] Bump integration test image to 18.0 by @fabianschuiki in #7895
• [FIRRTL] Make IMDCE work for ops w/ regions/blocks by @seldridge in #7881
• [circt-test] fix lit config for circt-bmc by @unlsycn in #7884
• [circt-bmc] Drop outdated integration test by @TaoBi22 in #7898
• [circt-bmc][VerifToSMT] Pop existing assertions on each cycle by @TaoBi22 in #7900
• [FIRRTL] Cleanup transform includes, NFC by @seldridge in #7901
• [circt-test] fix lit config for circt-bmc by @unlsycn in #7897
• SCF IndexSwitch to nested If-Else by @jiahanxie353 in #7905
• [FIRRTL] Remove all traces of OMIR JSON support. by @mikeurbach in #7907
• [DC] Add CAPI bindings for DC by @teqdruid in #7906
• [FIRRTL] Rip out OMIRTracker and logic that uses it. by @mikeurbach in #7908
• [SCFToCalyx] remove redundant build switch group by @jiahanxie353 in #7910
• [HandshakeToDC] Getting some working tests by @teqdruid in #7858
• [PyCDE][Handshake] Add bindings for Handshake functions by @teqdruid in #7849
• [FIRRTL] FoldRegMems: insert new ops into same block as memory by @rwy7 in #7909
• [HW] ExportHier: do not include bound in modules by @youngar in #7915
• [ImportVerilog] add stream concat operation by @chenbo-again in #7784
• [FIRRTL] FoldUnusedBits: Cast compressed data back to signed integer by @rwy7 in #7913
• [FIRRTL] FoldUnusedBits: minor cleanup by @rwy7 in #7914
• [Calyx] Lower Arith CmpFOp to Calyx by @jiahanxie353 in #7860
• [HWToSMT] ArrayCreateOp and ArrayGetOp support by @maerhart in #7666
• [circt-bmc] Add a simple test with a register storing an aggregate by @maerhart in #7922
• [circt-bmc][VerifToSMT] Add initial value support by @TaoBi22 in #7903
• [Calyx] Avoid using designated initializers by @TaoBi22 in #7926
• [VerifToSMT] Exit early after too many clocks error by @TaoBi22 in #7923
• [SMT] Add set_logic operation by @TaoBi22 in #7927
• [FIRRTL] Support layers in MergeConnections by @seldridge in #7912
• Fix URL for firrtl spec by @sequencer in #7919
• [RTG] Add TestOp, TargetOp, and DictType by @maerhart in #7856

New Contributors

• @unlsycn made their first contribution in #7884
• @chenbo-again made their first contribution in #7784

Full Changelog: firtool-1.95.1...firtool-1.96.0