[rtl] Guard against false memory responses for secure configurations #140
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1 error and 1 warning
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rtl/ibex_ex_block.sv#L208
[verible-verilog-lint] reported by reviewdog 🐶
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw Output:
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./rtl/ibex_ex_block.sv" range:{start:{line:208 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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