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[rtl] Guard against false memory responses for secure configurations #2166

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merged 1 commit into from
Jun 4, 2024

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GregAC
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@GregAC GregAC commented May 16, 2024

With this change all memory responses are only acted on if Ibex is expecting them for all secure configurations. Previously an error response that was injected onto the bus would trigger an exception that shouldn't occur (in particular breaking the functioning of the multiply state machine). In addition for configurations without the writeback stage an injected load data response could trigger an incorrect write to the register file.

This is only applied to the secure configurations, non-secure configurations assume correct adherence to the bus protocol meaning a response will only be seen if a request is outstanding.

Fixes #2144

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@marnovandermaas marnovandermaas left a comment

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I think this change looks reasonable to me, although it would be good to get more people to approve before merging.

@GregAC GregAC force-pushed the mem_response_check branch from 2e34f95 to 74e2196 Compare May 16, 2024 15:31
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Very nice work, many thanks @GregAC !

assign sva_multdiv_fsm_idle = 1'b1;
end

// Mark the sva_multduv_fsm_idle as unused to avoid lint issues
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Mintor typo: sva_multduv_fsm_idle -> sva_multdiv_fsm_idle

@@ -1810,6 +1839,9 @@ module ibex_core import ibex_pkg::*; #(
// Certain parameter combinations are not supported
`ASSERT_INIT(IllegalParamSecure, !(SecureIbex && (RV32M == RV32MNone)))

// If the ID stage signals its ready the mult/div FSMs must be idle in the following cycle
`ASSERT(MultDivFSMIdleOnIdReady, id_in_ready |=> ex_block_i.sva_multdiv_fsm_idle)
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ex_block_i.sva_multdiv_fsm_idle is not accessible if INC_ASSERT is not defined

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This is true but ASSERT is just an empty macro when INC_ASSERT isn't defined so this doesn't cause an issue.

@GregAC GregAC force-pushed the mem_response_check branch from 74e2196 to 8fe62ea Compare June 4, 2024 09:22
With this change all memory responses are only acted on if Ibex is
expecting them for all secure configurations. Previously an error
response that was injected onto the bus would trigger an exception that
shouldn't occur (in particular breaking the functioning of the multiply
state machine). In addition for configurations without the writeback
stage an injected load data response could trigger an incorrect write to
the register file.

This is only applied to the secure configurations, non-secure
configurations assume correct adherence to the bus protocol meaning a
response will only be seen if a request is outstanding.
@GregAC GregAC force-pushed the mem_response_check branch from 8fe62ea to 2fc670d Compare June 4, 2024 09:24
@GregAC GregAC added this pull request to the merge queue Jun 4, 2024
Merged via the queue into lowRISC:master with commit 5977d4e Jun 4, 2024
11 checks passed
@GregAC GregAC deleted the mem_response_check branch June 4, 2024 12:00
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Security vulnerability: Ibex leaks data when multiplication is aborted
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