Release procedure move to use sim test runner

doc/dev/release-procedure.md

@@ -62,10 +62,13 @@ cp sonata-vX.Y.bit.slot3.uf2 ../
 
 ### Automated testing
 
-Run tests on FPGA (note python3.11 or above required), adjust the /dev part to the UART as required.
+Run tests on simulation (note python3.11 or above required). FPGA testing is currently done in CI and requires quite a few add-ons to your board.
 
 ```shell
-./util/test_runner.py fpga -e ./sw/cheri/build/tests/test_runner -t ./util/sonata-openocd-cfg.tcl /dev/ttyUSB2
+# Build the simulator
+fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:sonata:system
+# Run the tests
+util/test_runner.py sim -e sw/cheri/build/tests/test_runner --simulator-binary build/lowrisc_sonata_system_0/sim-verilator/Vtop_verilator
 ```
 
 ### Bare-metal testing