Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Release procedure update #342

Merged
merged 7 commits into from
Nov 28, 2024
Merged

Release procedure update #342

Changes from 6 commits
Commits
Show all changes
7 commits
Select commit Hold shift + click to select a range
b39e051
Release procedure add sim test runner
marnovandermaas Nov 8, 2024
f591a73
Release procedure USB testing
marnovandermaas Nov 8, 2024
5a24b17
Release procedure general checks added
marnovandermaas Nov 8, 2024
82671ea
Release procedure bootloader update
marnovandermaas Nov 8, 2024
f08e778
Release procedure update Snake to slot 2
marnovandermaas Nov 8, 2024
e12c161
Release notes update release files
marnovandermaas Nov 8, 2024
10f0ba4
Release procedure one sentence per line
marnovandermaas Nov 13, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
78 changes: 71 additions & 7 deletions doc/dev/release-procedure.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,16 @@ cp sonata-vX.Y.bit.slot3.uf2 ../

### Automated testing

Run tests on FPGA (note python3.11 or above required), adjust the /dev part to the UART as required.
Run tests on simulation (note python3.11 or above required). FPGA testing is currently done in CI and requires quite a few add-ons to your board.
marnovandermaas marked this conversation as resolved.
Show resolved Hide resolved
marnovandermaas marked this conversation as resolved.
Show resolved Hide resolved

```shell
# Build the simulator
fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:sonata:system
# Run the tests
util/test_runner.py sim -e sw/cheri/build/tests/test_runner --simulator-binary build/lowrisc_sonata_system_0/sim-verilator/Vtop_verilator
```

Run tests on FPGA (note python3.11 or above required), adjust the /dev part to the UART as required. You will need to connect a Raspberry Pi sense HAT and a temperature sensor to QWIIC 1.
marnovandermaas marked this conversation as resolved.
Show resolved Hide resolved

```shell
./util/test_runner.py fpga -e ./sw/cheri/build/tests/test_runner -t ./util/sonata-openocd-cfg.tcl /dev/ttyUSB2
Expand Down Expand Up @@ -105,6 +114,57 @@ Got second flash read:
80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
```

Run the USB connection test:
```shell
util/mem_helper.sh load_program -e sw/cheri/build/checks/usbdev_check
```
Connect the user USB to a laptop's USB-A port. The UART should show this:
```
Initialising USB
Connected
Test passed; disconnected from USB.
```

Run the USB echo test. First you need to apply the following diff:
```diff
diff --git a/sw/cheri/checks/usbdev_check.cc b/sw/cheri/checks/usbdev_check.cc
index 4212ae7..7c68507 100644
--- a/sw/cheri/checks/usbdev_check.cc
+++ b/sw/cheri/checks/usbdev_check.cc
@@ -26,7 +26,7 @@ using namespace CHERI;
// - if disconnection is not enabled then a terminator emulator may be attached to `/dev/ttyUSB<n>`
// and a sign-on message should be observed. Any characters entered into the terminal will
// be echoed on the UART output.
-static constexpr bool do_disconnect = true;
+static constexpr bool do_disconnect = false;

static void write_strn(UartPtr uart, const char *str, size_t len) {
while (len-- > 0u) {
```
Then use the following commands:
```shell
cmake --build sw/cheri/build
util/mem_helper.sh load_program -e sw/cheri/build/checks/usbdev_check
```

Check the UART output is:
```
Initialising USB
Connected
Sent sign-on message over USB.
```

Open USB serial output. For me this is `screen /dev/ttyUSB1`. Check that the output is:
```
Hello from CHERI USB!
```
Also type into the USB screen instance and see that it is echoed on the UART side.

Here are some checks that you should also do for which there are no detailed instructions:
- Check the Ethernet is working.
- Check the manual pinmux test over PMOD.
- Check the RS-485 is working.

#### Vivado - Known errors

None at the moment.
Expand Down Expand Up @@ -153,9 +213,11 @@ Open screen:
screen /dev/ttyUSB2 921600
```

You should see output from the simple demo after you press the reset button (SW5):
You should see output from the simple demo after you press the reset button (SW5). The git SHA will depend on the commit your built your bitstream on, please confirm this is the same as you expect.

```
bootloader: Sonata system git SHA: 9f794fe3bd4eec8d
bootloader: Selected software slot: 1
bootloader: Loading software from flash...
bootloader: Booting into program, hopefully.
Led Walk Raw: Look pretty LEDs!
Expand Down Expand Up @@ -201,13 +263,13 @@ These values will change as you move your hand over the proximity sensor.

### Snake demo

Load snake demo and play snake:
Load snake demo, set your software switch to 2 and play snake:

```shell
# Copy to parent release dir
cp ./build/cheriot/cheriot/release/snake_demo.slot1.uf2 ../snake_demo_vX.Y.slot1.uf2
cp ./build/cheriot/cheriot/release/snake_demo.slot2.uf2 ../snake_demo_vX.Y.slot2.uf2
# Program onto the FPGA
cp ../snake_demo_vX.Y.slot1.uf2 /path/to/SONATA/
cp ../snake_demo_vX.Y.slot2.uf2 /path/to/SONATA/
```

Check that you see capability the exception LEDs light up and fade out when you hit the game boundaries ('tag' exception for top and left boundaries, 'bounds' exception for bottom and right boundaries).
Expand Down Expand Up @@ -246,8 +308,10 @@ Test runner: All tests finished in 42895559 cycles

In your release directory from the procedures above you should have:
- `sonata-vX.Y.bit.slot1.uf2`
- `sonata-vX.Y.bit.slot2.uf2`
- `sonata-vX.Y.bit.slot3.uf2`
- `sonata_simple_demo_vX.Y.slot1.uf2`
- `snake_demo_vX.Y.slot1.uf2`
- `snake_demo_vX.Y.slot2.uf2`

Use these to create the GitHub release, remember to include the RP2040 UF2 and include appropriate release notes.

Expand Down Expand Up @@ -303,4 +367,4 @@ An example release notes looks something like this:
> 5. Once programming is successful, you should see the "CHERI" LED light up and the "LEGACY" LED turn off. If this is not the case, the bitstream loading may have failed and you should retry by unplugging and replugging the main USB on the Sonata board. Then re-drag the bitstream into the "SONATA" drive.
> 6. After programming the bitstream, drag the `sonata_simple_demo_vX.Y.slot1.uf2` into the "SONATA" drive.
> 7. You should now see the user LEDs turn on and off, as well as the lowRISC logo appear on the LCD.
> 8. You can also drag `snake_demo_vX.Y.slot1.uf2` into the SONATA drive to play snake using the joystick. Watch the CHERI error LEDs as you hit the boundary.
> 8. You can also drag `snake_demo_vX.Y.slot2.uf2` into the SONATA drive to play snake using the joystick. Make sure to switch to the second software slot (SW7) and reset the board with SW5. Watch the CHERI error LEDs as you hit the boundary.
Loading