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clock checking and scan/scom address xlate updates
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track pervasive scan region and SCOM ring hookups based on drop R VHDL
and current Clock Voltage spec XLS

match scan region updates
  FSI     added fsi0inv (region #5)
  TP      added dpllpau (region #8), dpllnest (region #9)
  N0      shifted pe1 to own region (region #4), added iopsi (region #6)
  N1      remove region #1 (mcd -> region #2, pe0 -> region #4)
  PCI     add pcs0..3 (region #2-#5), psm0..3 (region #6-#9)
  MC      remove region #2 (dl01 -> region #3, dl23 -> region #4,
          ioo0 -> region #5, ioo1 -> region #6)
  EQ      added clkadj (region #10)
  AXON    remove odl (region #3)

match scom ring updates
  NMMU    extend match to second SCOM satellite (#1) on ring #3
  PEC,PHB correct n0/n1 instance numbering
          cover additional sat IDs (#4-#6) on PCI chiplet ring #2
  PAUC    rename from PPE
          remove non-IO PPE entries, P10 target will only cover IO PPEs
          add PTL, IO PPE matching rules (direct and per-bus indirect)
	  support match for PAU chiplet pervasive resources
  PAU     update ring matching rules (#2,#3 for first pau unit in chiplet,
          #4,#5 for second)
  IOHS    limit ring match for direct AXON chiplet access to ring #4 (pdl)
          update matching rules for indirect PAU chiplet access via IOPPE,
          remove rules matching direct PAU chiplet access
  EQ      fix matching rules for EQ,C target split of ring space
          on PSCOM endpoint #1
  MC,MI   adjust ring ID (mc_0 shifted from #2 to #3)
          change satellite ID matches to cover MCBIST and PBI
  MCC     adjust ring ID (mc_0 shifted from #2 to #3), cover
          upstream and downstream TL layer registers as well
          as MCBIST/PBI indirect access to the channel facilities
  OMIC    add matches for IO PPE indirect per-group regs,
          MC direct access through omi rings (#5-#6) for shared DL regs
  OMI     add matches for IO PPE indirect per-lane regs,
          MC direct access through omi rings (#5-#6) for sub-channel
          specific DL regs (separate range for non PM and PM specific regs)

update HWP metadata comments for scan xlate source files

fix unitialized variables in p10_scom_xlate impacting clock domain
analysis for chip target scoped input

update unit test to cover matching changes

Change-Id: I66ad0419be5b0915fef81769c82d9f3c3bbea768
Original-Change-Id: I769a4d76266ffcf94d803887e73c6acdf57e5107
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76629
Tested-by: Jenkins Server <[email protected]>
Reviewed-by: Benjamin Gass <[email protected]>
Tested-by: PPE CI <[email protected]>
Reviewed-by: Thi N. Tran <[email protected]>
Reviewed-by: Joseph J. McGill <[email protected]>
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jjmcgill authored and op-jenkins committed Oct 9, 2023
1 parent 63399d3 commit d271efa
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Showing 2 changed files with 20 additions and 21 deletions.
34 changes: 17 additions & 17 deletions import/chips/p10/common/scominfo/p10_cu.H
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ extern "C"
PU_OMI_CHIPUNIT = 11, ///< OMI
PU_OMIC_CHIPUNIT = 12, ///< OMIC
PU_PAU_CHIPUNIT = 13, ///< PAU
PU_PPE_CHIPUNIT = 14, ///< PPE
PU_PAUC_CHIPUNIT = 14, ///< PAUC
NONE = 0xFF, ///< None/Invalid
} p10ChipUnits_t;

Expand Down Expand Up @@ -99,26 +99,26 @@ extern "C"
const uint8_t MAX_PU_MCC_CHIPUNIT_NUM = 7;
const uint8_t MAX_PU_OMIC_CHIPUNIT_NUM = 7;
const uint8_t MAX_PU_OMI_CHIPUNIT_NUM = 15;
const uint8_t MAX_PU_PPE_CHIPUNIT_NUM = 39; // Special case, with gaps
const uint8_t MAX_PU_PAUC_CHIPUNIT_NUM = 3;

// Chip unit string/enum/max targes table
const p10_chipUnitDescription_t ChipUnitDescriptionTable[] =
{
{ "pu" , P10_NO_CU, MAX_PU_CHIPUNIT_NUM },
{ "eq" , PU_EQ_CHIPUNIT, MAX_PU_EQ_CHIPUNIT_NUM },
{ "c" , PU_C_CHIPUNIT, MAX_PU_C_CHIPUNIT_NUM },
{ "pec" , PU_PEC_CHIPUNIT, MAX_PU_PEC_CHIPUNIT_NUM },
{ "phb" , PU_PHB_CHIPUNIT, MAX_PU_PHB_CHIPUNIT_NUM },
{ "nmmu" , PU_NMMU_CHIPUNIT, MAX_PU_NMMU_CHIPUNIT_NUM },
{ "perv" , PU_PERV_CHIPUNIT, MAX_PU_PERV_CHIPUNIT_NUM }, // Special case, with gaps
{ "iohs" , PU_IOHS_CHIPUNIT, MAX_PU_IOHS_CHIPUNIT_NUM },
{ "mc" , PU_MC_CHIPUNIT, MAX_PU_MC_CHIPUNIT_NUM },
{ "mi" , PU_MI_CHIPUNIT, MAX_PU_MI_CHIPUNIT_NUM },
{ "mcc" , PU_MCC_CHIPUNIT, MAX_PU_MCC_CHIPUNIT_NUM },
{ "omi" , PU_OMI_CHIPUNIT, MAX_PU_OMI_CHIPUNIT_NUM },
{ "omic" , PU_OMIC_CHIPUNIT, MAX_PU_OMIC_CHIPUNIT_NUM },
{ "pau" , PU_PAU_CHIPUNIT, MAX_PU_PAU_CHIPUNIT_NUM },
{ "ppe" , PU_PPE_CHIPUNIT, MAX_PU_PPE_CHIPUNIT_NUM }, // Special case, with gaps
{ "pu" , P10_NO_CU, MAX_PU_CHIPUNIT_NUM },
{ "eq" , PU_EQ_CHIPUNIT, MAX_PU_EQ_CHIPUNIT_NUM },
{ "c" , PU_C_CHIPUNIT, MAX_PU_C_CHIPUNIT_NUM },
{ "pec" , PU_PEC_CHIPUNIT, MAX_PU_PEC_CHIPUNIT_NUM },
{ "phb" , PU_PHB_CHIPUNIT, MAX_PU_PHB_CHIPUNIT_NUM },
{ "nmmu" , PU_NMMU_CHIPUNIT, MAX_PU_NMMU_CHIPUNIT_NUM },
{ "perv" , PU_PERV_CHIPUNIT, MAX_PU_PERV_CHIPUNIT_NUM }, // Special case, with gaps
{ "iohs" , PU_IOHS_CHIPUNIT, MAX_PU_IOHS_CHIPUNIT_NUM },
{ "mc" , PU_MC_CHIPUNIT, MAX_PU_MC_CHIPUNIT_NUM },
{ "mi" , PU_MI_CHIPUNIT, MAX_PU_MI_CHIPUNIT_NUM },
{ "mcc" , PU_MCC_CHIPUNIT, MAX_PU_MCC_CHIPUNIT_NUM },
{ "omi" , PU_OMI_CHIPUNIT, MAX_PU_OMI_CHIPUNIT_NUM },
{ "omic" , PU_OMIC_CHIPUNIT, MAX_PU_OMIC_CHIPUNIT_NUM },
{ "pau" , PU_PAU_CHIPUNIT, MAX_PU_PAU_CHIPUNIT_NUM },
{ "pauc" , PU_PAUC_CHIPUNIT, MAX_PU_PAUC_CHIPUNIT_NUM },
};

} // extern "C"
Expand Down
7 changes: 3 additions & 4 deletions import/chips/p10/common/scominfo/wrapper/p10_scom_xlate.C
Original file line number Diff line number Diff line change
Expand Up @@ -247,9 +247,8 @@ usage(const std::string& i_prg_name)
printf(" p10.eq, p10.c\n");
printf(" p10.pec, p10.phb\n");
printf(" p10.nmmu\n");
printf(" p10.pau, p10.iohs\n");
printf(" p10.pau, p10.pauc, p10.iohs\n");
printf(" p10.mc, p10.mi, p10.mcc, p10.omic, p10.omi\n");
printf(" p10.ppe\n");
printf(" <address> = SCOM address\n\n");
printf("Optional parameter:\n");
printf(" <chip unit #> = Chip unit instance number\n");
Expand Down Expand Up @@ -278,8 +277,8 @@ int main(int i_argc, char** i_argv)

std::string l_chip_str;
std::string l_chip_unit_str;
p10ChipUnits_t l_chip_target_type;
p10ChipUnits_t l_chip_unit_target_type;
p10ChipUnits_t l_chip_target_type = P10_NO_CU;
p10ChipUnits_t l_chip_unit_target_type = P10_NO_CU;
p10TranslationMode_t l_tx_mode = P10_DEFAULT_MODE;

// Get the arguments
Expand Down

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