doc: Minimally describe the BSCAN tunnel interface.

Add minimal documentation for the BSCAN tunnel interface.
This is based on Tim Newsome <[email protected]>'s work on
the RISC-V fork.

Change-Id: I5e0cd6972cb90649670249765e9bb30c2847eea6
Signed-off-by: Tim Newsome <[email protected]>
Signed-off-by: Bernhard Rosenkränzer <[email protected]>
Reviewed-on: https://review.openocd.org/c/openocd/+/8297
Tested-by: jenkins
Reviewed-by: Antonio Borneo <[email protected]>

doc/openocd.texi

@@ -11279,8 +11279,22 @@ and DBUS registers, respectively.
 @end deffn
 
 @deffn {Command} {riscv use_bscan_tunnel} value
-Enable or disable use of a BSCAN tunnel to reach DM.  Supply the width of
-the DM transport TAP's instruction register to enable.  Supply a value of 0 to disable.
+Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
+width of the DM transport TAP's instruction register to enable. Supply a
+value of 0 to disable.
+
+This BSCAN tunnel interface is specific to SiFive IP. Anybody may implement
+it, but currently there is no good documentation on it. In a nutshell, this
+feature scans USER4 into a Xilinx TAP to select the tunnel device (assuming
+hardware is present and it is hooked up to the Xilinx USER4 IR) and
+encapsulates a tunneled scan directive into a DR scan into the Xilinx TAP. A
+tunneled DR scan consists of:
+@enumerate
+@item 1 bit that selects IR when 0, or DR when 1
+@item 7 bits that encode the width of the desired tunneled scan
+@item A width+1 stream of bits for the tunneled TDI. The plus one is because there is a one-clock skew between TDI of Xilinx chain and TDO from tunneled chain.
+@item 3 bits of zero that the tunnel uses to go back to idle state.
+@end enumerate
 @end deffn
 
 @deffn {Command} {riscv set_ebreakm} on|off