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pzbcm_slicer
Taichi Ishitani edited this page Dec 26, 2022
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2 revisions
https://github.com/pezy-computing/pzbcm/tree/master/pzbcm_slicer
This module is a slicer module to insert series of slicer units for ease of timing closure. Data through this module is transferred by using the valid/ready handshake scheme.
| name | type/width | default value |
|---|---|---|
| WIDTH | int | 1 |
| TYPE | type | logic[WIDTH-1:0] |
| STAGES | int | 1 |
| FULL_BANDWIDTH | bit | 1 |
| DISABLE_MBFF | bit | 0 |
- WIDTH/TYPE
- Type/Width of data through this module.
- STAGES
- Specify number of slicer units will be instantiated in this module.
- FULL_BANDWIDTH
- Bandwidth of this module is full bandwidth if this value set to 1.
- Bandwidth of this module is half bandwidth if this value set to 0.
- DISABLE_MBFF
- When this value is set to 1 inferring multi bit FF cell by a synthesis tool is forcely disabled.
| name | direction | type/width | note |
|---|---|---|---|
| i_clk | input | 1 | clock |
| i_rst_n | input | 1 | reset (async/active low) |
| i_valid | input | 1 | indicate i_data is valid |
| o_ready | output | 1 | indicate this module can accept i_data
|
| i_data | input | TYPE | input data |
| o_valid | output | 1 | indicate o_data is valid |
| i_ready | input | 1 | indicate the output side can accept o_data
|
| o_data | output | TYPE | output data |