Merge pull request #49 from changab/Ratified_V1.0.0

Ratified v1.0.0
riscv · Mar 12, 2023 · f8ec1b7 · f8ec1b7
2 parents 4da42ab + c3f92c8
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diff --git a/changelog.adoc b/changelog.adoc
@@ -7,6 +7,10 @@
 [preface]
 == Change Log
 
+=== version 1.0.0
+* 2023-3-11
+** Ratified version
+
 === version 1.0.0_rc6
 * 2023-1-5
 ** Remove H/U mode from this spec.

diff --git a/licensing.adoc b/licensing.adoc
@@ -8,7 +8,7 @@
 [Preface]
 == Copyright and license information
 
-This RISC-V PLIC specification is © 2017-2022 RISC-V international
+This RISC-V PLIC specification is © 2017-2023 RISC-V international
 
 This document is released under a Creative Commons Attribution 4.0
 International License. +

diff --git a/riscv-plic-1.0.0.pdf b/riscv-plic-1.0.0.pdf
diff --git a/riscv-plic.adoc b/riscv-plic.adoc
@@ -2,9 +2,9 @@
 
 :description: RISC-V PLIC Specification
 :company: RISC-V.org
-:revdate: 10/2022
-:revnumber: 1.0.0_rc5
-:revremark: This document is in Frozen state. Change is extremely unlikely. See http://riscv.org/spec-state for details.
+:revdate: 3/2023
+:revnumber: 1.0.0
+:revremark: This document is in Ratified state. No changes are allowed. See http://riscv.org/spec-state for details.
 :url-riscv: http://riscv.org
 :doctype: book
 :preface-title: Preamble
@@ -42,12 +42,10 @@ RISC-V Task Group
 
 // Preamble
 [WARNING]
-.This document is in the link:http://riscv.org/spec-state[Frozen state]
+.This document is in the link:http://riscv.org/spec-state[Ratified state]
 ====
-Change is extremely unlikely. A high threshold will be used, and a change will
-only occur because of some truly critical issue being identified during the
-public review cycle. Any other desired or needed changes can be the subject
-of a follow-on new extension.
+No changes are allowed. Any desired or needed changes can be the subject
+of a follow-on new extension. Ratified extensions are never revised
 ====
 
 // changelog of the document
@@ -104,7 +102,7 @@ image::PLIC.jpg[400,432,align="center"]
 === Interrupt Gateways
 
 The interrupt gateways are responsible for converting global interrupt signals 
-into a common interrupt request format, and for controlling the ﬂow of interrupt
+into a common interrupt request format, and for controlling the flow of interrupt
 requests to the PLIC core. At most one interrupt request per interrupt source can
 be pending in the PLIC core at any time, indicated by setting the source's IP bit.
 The gateway only forwards a new interrupt request to the PLIC core after receiving