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fixup: i2c: restrict access to TAR register #10

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Oct 16, 2023
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fixup: i2c: restrict access to TAR register #10

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2 changes: 1 addition & 1 deletion cmsis-svd-generator
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Submodule cmsis-svd-generator updated 16 files
+20 −0 README.md
+125 −6 generate_svd.py
+102 −0 regmaps/starfive_jh7110_pwm.svd
+423 −0 scripts/arm_pl022.py
+172 −0 scripts/snps_designware_i2c.py
+333 −0 scripts/starfive_common.py
+203 −0 scripts/starfive_jh7110_aon_pinctrl.py
+120 −0 scripts/starfive_jh7110_aon_syscon.py
+37 −0 scripts/starfive_jh7110_aoncrg.py
+157 −0 scripts/starfive_jh7110_pmu.py
+1,077 −0 scripts/starfive_jh7110_stg_syscon.py
+55 −0 scripts/starfive_jh7110_stgcrg.py
+246 −0 scripts/starfive_jh7110_sys_pinctrl.py
+675 −0 scripts/starfive_jh7110_sys_syscon.py
+221 −0 scripts/starfive_jh7110_syscrg.py
+326 −0 scripts/starfive_jh7110_trng.py
42 changes: 21 additions & 21 deletions jh7110-vf2-12a-pac/jh7110-starfive-visionfive-2-v1.2a.svd
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Expand Up @@ -256,9 +256,9 @@
<size>32</size>
<fields>
<field>
<name>tar</name>
<description>tar</description>
<bitRange>[31:0]</bitRange>
<name>master_10bit</name>
<description>If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
Expand Down Expand Up @@ -1284,9 +1284,9 @@
<size>32</size>
<fields>
<field>
<name>tar</name>
<description>tar</description>
<bitRange>[31:0]</bitRange>
<name>master_10bit</name>
<description>If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
Expand Down Expand Up @@ -2312,9 +2312,9 @@
<size>32</size>
<fields>
<field>
<name>tar</name>
<description>tar</description>
<bitRange>[31:0]</bitRange>
<name>master_10bit</name>
<description>If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
Expand Down Expand Up @@ -9952,9 +9952,9 @@
<size>32</size>
<fields>
<field>
<name>tar</name>
<description>tar</description>
<bitRange>[31:0]</bitRange>
<name>master_10bit</name>
<description>If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
Expand Down Expand Up @@ -10980,9 +10980,9 @@
<size>32</size>
<fields>
<field>
<name>tar</name>
<description>tar</description>
<bitRange>[31:0]</bitRange>
<name>master_10bit</name>
<description>If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
Expand Down Expand Up @@ -12008,9 +12008,9 @@
<size>32</size>
<fields>
<field>
<name>tar</name>
<description>tar</description>
<bitRange>[31:0]</bitRange>
<name>master_10bit</name>
<description>If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
Expand Down Expand Up @@ -13036,9 +13036,9 @@
<size>32</size>
<fields>
<field>
<name>tar</name>
<description>tar</description>
<bitRange>[31:0]</bitRange>
<name>master_10bit</name>
<description>If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
Expand Down
20 changes: 10 additions & 10 deletions jh7110-vf2-12a-pac/src/snps_designware_i2c_0/tar.rs
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Expand Up @@ -2,23 +2,23 @@
pub type R = crate::R<TAR_SPEC>;
#[doc = "Register `tar` writer"]
pub type W = crate::W<TAR_SPEC>;
#[doc = "Field `tar` reader - tar"]
pub type TAR_R = crate::FieldReader<u32>;
#[doc = "Field `tar` writer - tar"]
pub type TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>;
#[doc = "Field `master_10bit` reader - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_R = crate::BitReader;
#[doc = "Field `master_10bit` writer - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
impl R {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
pub fn tar(&self) -> TAR_R {
TAR_R::new(self.bits)
pub fn master_10bit(&self) -> MASTER_10BIT_R {
MASTER_10BIT_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
#[must_use]
pub fn tar(&mut self) -> TAR_W<TAR_SPEC, 0> {
TAR_W::new(self)
pub fn master_10bit(&mut self) -> MASTER_10BIT_W<TAR_SPEC, 12> {
MASTER_10BIT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand Down
20 changes: 10 additions & 10 deletions jh7110-vf2-12a-pac/src/snps_designware_i2c_1/tar.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,23 +2,23 @@
pub type R = crate::R<TAR_SPEC>;
#[doc = "Register `tar` writer"]
pub type W = crate::W<TAR_SPEC>;
#[doc = "Field `tar` reader - tar"]
pub type TAR_R = crate::FieldReader<u32>;
#[doc = "Field `tar` writer - tar"]
pub type TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>;
#[doc = "Field `master_10bit` reader - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_R = crate::BitReader;
#[doc = "Field `master_10bit` writer - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
impl R {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
pub fn tar(&self) -> TAR_R {
TAR_R::new(self.bits)
pub fn master_10bit(&self) -> MASTER_10BIT_R {
MASTER_10BIT_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
#[must_use]
pub fn tar(&mut self) -> TAR_W<TAR_SPEC, 0> {
TAR_W::new(self)
pub fn master_10bit(&mut self) -> MASTER_10BIT_W<TAR_SPEC, 12> {
MASTER_10BIT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand Down
20 changes: 10 additions & 10 deletions jh7110-vf2-12a-pac/src/snps_designware_i2c_2/tar.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,23 +2,23 @@
pub type R = crate::R<TAR_SPEC>;
#[doc = "Register `tar` writer"]
pub type W = crate::W<TAR_SPEC>;
#[doc = "Field `tar` reader - tar"]
pub type TAR_R = crate::FieldReader<u32>;
#[doc = "Field `tar` writer - tar"]
pub type TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>;
#[doc = "Field `master_10bit` reader - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_R = crate::BitReader;
#[doc = "Field `master_10bit` writer - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
impl R {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
pub fn tar(&self) -> TAR_R {
TAR_R::new(self.bits)
pub fn master_10bit(&self) -> MASTER_10BIT_R {
MASTER_10BIT_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
#[must_use]
pub fn tar(&mut self) -> TAR_W<TAR_SPEC, 0> {
TAR_W::new(self)
pub fn master_10bit(&mut self) -> MASTER_10BIT_W<TAR_SPEC, 12> {
MASTER_10BIT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand Down
20 changes: 10 additions & 10 deletions jh7110-vf2-12a-pac/src/snps_designware_i2c_3/tar.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,23 +2,23 @@
pub type R = crate::R<TAR_SPEC>;
#[doc = "Register `tar` writer"]
pub type W = crate::W<TAR_SPEC>;
#[doc = "Field `tar` reader - tar"]
pub type TAR_R = crate::FieldReader<u32>;
#[doc = "Field `tar` writer - tar"]
pub type TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>;
#[doc = "Field `master_10bit` reader - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_R = crate::BitReader;
#[doc = "Field `master_10bit` writer - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
impl R {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
pub fn tar(&self) -> TAR_R {
TAR_R::new(self.bits)
pub fn master_10bit(&self) -> MASTER_10BIT_R {
MASTER_10BIT_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
#[must_use]
pub fn tar(&mut self) -> TAR_W<TAR_SPEC, 0> {
TAR_W::new(self)
pub fn master_10bit(&mut self) -> MASTER_10BIT_W<TAR_SPEC, 12> {
MASTER_10BIT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand Down
20 changes: 10 additions & 10 deletions jh7110-vf2-12a-pac/src/snps_designware_i2c_4/tar.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,23 +2,23 @@
pub type R = crate::R<TAR_SPEC>;
#[doc = "Register `tar` writer"]
pub type W = crate::W<TAR_SPEC>;
#[doc = "Field `tar` reader - tar"]
pub type TAR_R = crate::FieldReader<u32>;
#[doc = "Field `tar` writer - tar"]
pub type TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>;
#[doc = "Field `master_10bit` reader - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_R = crate::BitReader;
#[doc = "Field `master_10bit` writer - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
impl R {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
pub fn tar(&self) -> TAR_R {
TAR_R::new(self.bits)
pub fn master_10bit(&self) -> MASTER_10BIT_R {
MASTER_10BIT_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
#[must_use]
pub fn tar(&mut self) -> TAR_W<TAR_SPEC, 0> {
TAR_W::new(self)
pub fn master_10bit(&mut self) -> MASTER_10BIT_W<TAR_SPEC, 12> {
MASTER_10BIT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand Down
20 changes: 10 additions & 10 deletions jh7110-vf2-12a-pac/src/snps_designware_i2c_5/tar.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,23 +2,23 @@
pub type R = crate::R<TAR_SPEC>;
#[doc = "Register `tar` writer"]
pub type W = crate::W<TAR_SPEC>;
#[doc = "Field `tar` reader - tar"]
pub type TAR_R = crate::FieldReader<u32>;
#[doc = "Field `tar` writer - tar"]
pub type TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>;
#[doc = "Field `master_10bit` reader - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_R = crate::BitReader;
#[doc = "Field `master_10bit` writer - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
impl R {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
pub fn tar(&self) -> TAR_R {
TAR_R::new(self.bits)
pub fn master_10bit(&self) -> MASTER_10BIT_R {
MASTER_10BIT_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
#[must_use]
pub fn tar(&mut self) -> TAR_W<TAR_SPEC, 0> {
TAR_W::new(self)
pub fn master_10bit(&mut self) -> MASTER_10BIT_W<TAR_SPEC, 12> {
MASTER_10BIT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand Down
20 changes: 10 additions & 10 deletions jh7110-vf2-12a-pac/src/snps_designware_i2c_6/tar.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,23 +2,23 @@
pub type R = crate::R<TAR_SPEC>;
#[doc = "Register `tar` writer"]
pub type W = crate::W<TAR_SPEC>;
#[doc = "Field `tar` reader - tar"]
pub type TAR_R = crate::FieldReader<u32>;
#[doc = "Field `tar` writer - tar"]
pub type TAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>;
#[doc = "Field `master_10bit` reader - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_R = crate::BitReader;
#[doc = "Field `master_10bit` writer - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
pub type MASTER_10BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
impl R {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
pub fn tar(&self) -> TAR_R {
TAR_R::new(self.bits)
pub fn master_10bit(&self) -> MASTER_10BIT_R {
MASTER_10BIT_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:31 - tar"]
#[doc = "Bit 12 - If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing mode has to be enabled via bit 12 of TAR register. We set it always as I2C_DYNAMIC_TAR_UPDATE can't be detected from registers."]
#[inline(always)]
#[must_use]
pub fn tar(&mut self) -> TAR_W<TAR_SPEC, 0> {
TAR_W::new(self)
pub fn master_10bit(&mut self) -> MASTER_10BIT_W<TAR_SPEC, 12> {
MASTER_10BIT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
Expand Down
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