riscv: define mie using CSR macros

Uses CSR helper macros to define the `mie` register.

riscv/src/register/mie.rs

@@ -1,56 +1,47 @@
 //! mie register
 
-/// mie register
-#[derive(Clone, Copy, Debug)]
-pub struct Mie {
-    bits: usize,
+read_write_csr! {
+    /// `mie` register
+    Mie: 0x304,
+    mask: 0xaaa,
 }
 
-impl Mie {
-    /// Returns the contents of the register as raw bits
-    #[inline]
-    pub fn bits(&self) -> usize {
-        self.bits
-    }
-
+read_write_csr_field! {
+    Mie,
     /// Supervisor Software Interrupt Enable
-    #[inline]
-    pub fn ssoft(&self) -> bool {
-        self.bits & (1 << 1) != 0
-    }
+    ssoft: 1,
+}
 
+read_write_csr_field! {
+    Mie,
     /// Machine Software Interrupt Enable
-    #[inline]
-    pub fn msoft(&self) -> bool {
-        self.bits & (1 << 3) != 0
-    }
+    msoft: 3,
+}
 
+read_write_csr_field! {
+    Mie,
     /// Supervisor Timer Interrupt Enable
-    #[inline]
-    pub fn stimer(&self) -> bool {
-        self.bits & (1 << 5) != 0
-    }
+    stimer: 5,
+}
 
+read_write_csr_field! {
+    Mie,
     /// Machine Timer Interrupt Enable
-    #[inline]
-    pub fn mtimer(&self) -> bool {
-        self.bits & (1 << 7) != 0
-    }
+    mtimer: 7,
+}
 
+read_write_csr_field! {
+    Mie,
     /// Supervisor External Interrupt Enable
-    #[inline]
-    pub fn sext(&self) -> bool {
-        self.bits & (1 << 9) != 0
-    }
+    sext: 9,
+}
 
+read_write_csr_field! {
+    Mie,
     /// Machine External Interrupt Enable
-    #[inline]
-    pub fn mext(&self) -> bool {
-        self.bits & (1 << 11) != 0
-    }
+    mext: 11,
 }
 
-read_csr_as!(Mie, 0x304);
 set!(0x304);
 clear!(0x304);