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Merge pull request #151 from rust-embedded/add-riscv-rt
Add riscv-rt to workspace
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name: Check Labels | ||
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on: | ||
pull_request: | ||
types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled] | ||
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jobs: | ||
label-check: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- uses: mheap/github-action-required-labels@v5 | ||
with: | ||
mode: exactly | ||
count: 0 | ||
labels: "work in progress, do not merge" | ||
add_comment: true | ||
message: "This PR is being prevented from merging because it presents one of the blocking labels: {{ provided }}." |
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on: | ||
push: | ||
branches: [ master ] | ||
pull_request: | ||
merge_group: | ||
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name: Build check (riscv-rt) | ||
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jobs: | ||
build: | ||
strategy: | ||
matrix: | ||
# All generated code should be running on stable now, MRSV is 1.59.0 | ||
toolchain: [ stable, nightly, 1.59.0 ] | ||
target: | ||
- riscv32i-unknown-none-elf | ||
- riscv32imc-unknown-none-elf | ||
- riscv32imac-unknown-none-elf | ||
- riscv64imac-unknown-none-elf | ||
- riscv64gc-unknown-none-elf | ||
example: | ||
- empty | ||
- multi_core | ||
include: | ||
# Nightly is only for reference and allowed to fail | ||
- toolchain: nightly | ||
experimental: true | ||
runs-on: ubuntu-latest | ||
continue-on-error: ${{ matrix.experimental || false }} | ||
steps: | ||
- uses: actions/checkout@v4 | ||
- uses: dtolnay/rust-toolchain@master | ||
with: | ||
toolchain: ${{ matrix.toolchain }} | ||
targets: ${{ matrix.target }} | ||
- name: Build (no features) | ||
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} | ||
- name : Build example (s-mode) | ||
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode | ||
- name : Build example (single-hart) | ||
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart | ||
- name: Build example (all features) | ||
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features | ||
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# Job to check that all the builds succeeded | ||
build-check: | ||
needs: | ||
- build | ||
runs-on: ubuntu-latest | ||
if: always() | ||
steps: | ||
- run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}' |
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resolver = "2" | ||
members = [ | ||
"riscv", | ||
"riscv-rt", | ||
] |
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[![crates.io](https://img.shields.io/crates/d/riscv.svg)](https://crates.io/crates/riscv) | ||
[![crates.io](https://img.shields.io/crates/v/riscv.svg)](https://crates.io/crates/riscv) | ||
[![Build Status](https://travis-ci.org/rust-embedded/riscv.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv) | ||
# RISC-V crates | ||
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# `riscv` | ||
This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers: | ||
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> Low level access to RISC-V processors | ||
* [`riscv`]: CPU peripheral access and intrinsics | ||
* [`riscv-rt`]: Startup code and interrupt handling | ||
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This project is developed and maintained by the [RISC-V team][team]. | ||
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## [Documentation](https://docs.rs/crate/riscv) | ||
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## Minimum Supported Rust Version (MSRV) | ||
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This crate is guaranteed to compile on stable Rust 1.60 and up. It *might* | ||
compile with older versions but that may change in any new patch release. | ||
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## License | ||
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Copyright 2019-2022 [RISC-V team][team] | ||
This project is developed and maintained by the [RISC-V team][team]. | ||
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Permission to use, copy, modify, and/or distribute this software for any purpose | ||
with or without fee is hereby granted, provided that the above copyright notice | ||
and this permission notice appear in all copies. | ||
### Contribution | ||
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH | ||
REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND | ||
FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, | ||
INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS | ||
OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | ||
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF | ||
THIS SOFTWARE. | ||
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the | ||
work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any | ||
additional terms or conditions. | ||
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## Code of Conduct | ||
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Contribution to this crate is organized under the terms of the [Rust Code of | ||
Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises | ||
to intervene to uphold that code of conduct. | ||
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[CoC]: CODE_OF_CONDUCT.md | ||
[`riscv`]: https://crates.io/crates/riscv | ||
[`riscv-rt`]: https://crates.io/crates/riscv-rt | ||
[team]: https://github.com/rust-embedded/wg#the-risc-v-team | ||
[CoC]: CODE_OF_CONDUCT.md |
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