mshv-ioctls: Add support for aarch64

Remove conditional compilation for x86_64. Signed-off-by: Jinank Jain <[email protected]>
rust-vmm · Mar 25, 2024 · 97c93da · 97c93da
1 parent 96f6653
commit 97c93da
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Showing 2 changed files with 12 additions and 1 deletion.
diff --git a/mshv-ioctls/src/ioctls/vcpu.rs b/mshv-ioctls/src/ioctls/vcpu.rs
@@ -564,6 +564,7 @@ impl VcpuFd {
         Ok(ret_regs)
     }
     /// X86 specific call that returns the vcpu's current "debug registers".
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn get_debug_regs(&self) -> Result<DebugRegisters> {
         let reg_names: [hv_register_name; 6] = [
             hv_register_name_HV_X64_REGISTER_DR0,
@@ -598,6 +599,7 @@ impl VcpuFd {
         Ok(ret_regs)
     }
     /// X86 specific call that sets the vcpu's current "debug registers".
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn set_debug_regs(&self, d_regs: &DebugRegisters) -> Result<()> {
         let reg_names = [
             hv_register_name_HV_X64_REGISTER_DR0,
@@ -630,6 +632,7 @@ impl VcpuFd {
         Ok(())
     }
     /// Returns the machine-specific registers (MSR) for this vCPU.
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn get_msrs(&self, msrs: &mut Msrs) -> Result<usize> {
         let nmsrs = msrs.as_fam_struct_ref().nmsrs as usize;
         let mut reg_assocs: Vec<hv_register_assoc> = Vec::with_capacity(nmsrs);
@@ -659,6 +662,7 @@ impl VcpuFd {
     }
     /// Setup the model-specific registers (MSR) for this vCPU.
     /// Returns the number of MSR entries actually written.
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn set_msrs(&self, msrs: &Msrs) -> Result<usize> {
         let nmsrs = msrs.as_fam_struct_ref().nmsrs as usize;
         let mut reg_assocs: Vec<hv_register_assoc> = Vec::with_capacity(nmsrs);
@@ -691,6 +695,7 @@ impl VcpuFd {
     }
     /// Returns currently pending exceptions, interrupts, and NMIs as well as related
     /// states of the vcpu.
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn get_vcpu_events(&self) -> Result<VcpuEvents> {
         let reg_names: [hv_register_name; 5] = [
             hv_register_name_HV_REGISTER_PENDING_INTERRUPTION,
@@ -721,6 +726,7 @@ impl VcpuFd {
         Ok(ret_regs)
     }
     /// Sets pending exceptions, interrupts, and NMIs as well as related states of the vcpu.
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn set_vcpu_events(&self, events: &VcpuEvents) -> Result<()> {
         let reg_names: [hv_register_name; 5] = [
             hv_register_name_HV_REGISTER_PENDING_INTERRUPTION,
@@ -764,6 +770,7 @@ impl VcpuFd {
         Ok(())
     }
     /// X86 specific call that returns the vcpu's current "xcrs".
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn get_xcrs(&self) -> Result<Xcrs> {
         let mut reg_assocs: [hv_register_assoc; 1] = [hv_register_assoc {
             name: hv_register_name_HV_X64_REGISTER_XFEM,
@@ -781,6 +788,7 @@ impl VcpuFd {
         Ok(ret_regs)
     }
     /// X86 specific call to set XCRs
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn set_xcrs(&self, xcrs: &Xcrs) -> Result<()> {
         self.set_reg(&[hv_register_assoc {
             name: hv_register_name_HV_X64_REGISTER_XFEM,
@@ -789,6 +797,7 @@ impl VcpuFd {
         }])
     }
     /// X86 specific call that returns the vcpu's current "misc registers".
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn get_misc_regs(&self) -> Result<MiscRegs> {
         let mut reg_assocs: [hv_register_assoc; 1] = [hv_register_assoc {
             name: hv_register_name_HV_X64_REGISTER_HYPERCALL,
@@ -806,6 +815,7 @@ impl VcpuFd {
         Ok(ret_regs)
     }
     /// X86 specific call that sets the vcpu's current "misc registers".
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn set_misc_regs(&self, misc: &MiscRegs) -> Result<()> {
         self.set_reg(&[hv_register_assoc {
             name: hv_register_name_HV_X64_REGISTER_HYPERCALL,
@@ -899,6 +909,7 @@ impl VcpuFd {
         Ok((gpa, result))
     }
     /// X86 specific call that returns the vcpu's current "suspend registers".
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn get_suspend_regs(&self) -> Result<SuspendRegisters> {
         let reg_names: [hv_register_name; 2] = [
             hv_register_name_HV_REGISTER_EXPLICIT_SUSPEND,
@@ -1054,6 +1065,7 @@ impl VcpuFd {
         Ok(*input)
     }
     /// Sets the sev control register
+    #[cfg(not(any(target_arch = "arm", target_arch = "aarch64")))]
     pub fn set_sev_control_register(&self, reg: u64) -> Result<()> {
         let reg_assocs = [hv_register_assoc {
             name: hv_register_name_HV_X64_REGISTER_SEV_CONTROL,

diff --git a/mshv-ioctls/src/lib.rs b/mshv-ioctls/src/lib.rs
@@ -2,7 +2,6 @@
 //
 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
 //
-#![cfg(target_arch = "x86_64")]
 #![allow(non_snake_case)]
 #![allow(non_upper_case_globals)]
 #![allow(non_camel_case_types)]