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The arguments in BufferedTx are flipped #12

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The arguments in BufferedTx are flipped #12

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5 changes: 2 additions & 3 deletions lab7/README.md
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Expand Up @@ -39,11 +39,10 @@ The UART component is a Chisel module. You can instantiate it with the
following code:

```scala
val uart = Module(new BufferedTx(115200, 100000000))
val uart = Module(new BufferedTx(100000000, 115200))
```

The first parameter is the baud rate, the second parameter is the clock
frequency. The ```BufferedTx``` component has a read/valid interface to
The first parameter is the clock frequency, the second parameter is the baud rate. The ```BufferedTx``` component has a read/valid interface to
send characters to the UART.

To see the output of the UART you need to connect it to a terminal program.
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