Add Cache Flush functionality to memHierarchy

Standardize memHierarchy port and port-subcomponent names
Fix several bugs in noninclusive coherence protocols
Fix case mismatch in merlin parameter
Add some missing statistics in memHierarchy coherence protocols
Remove some old unused parameters from memH components
Improve error checking in memH cache construction
Add memHierarchy README
Add new memHierarchy testing
Began prototype for eventual memHierarchy python module

src/sst/elements/ariel/frontend/simple/examples/multicore.py

@@ -46,7 +46,7 @@
         "L1" : 1,
     } )
     ariel_l1d_link = sst.Link("cpu_cache_link_" + str(x))
-    ariel_l1d_link.connect( (ariel, "cache_link_" + str(x), "50ps"), (l1d, "high_network_0", "50ps") )
+    ariel_l1d_link.connect( (ariel, "cache_link_" + str(x), "50ps"), (l1d, "highlink", "50ps") )
 
     # Private L2s
     # 128KB, 8-way set associative, 64B line, 5 cycle access
@@ -63,10 +63,10 @@
     })
 
     l1d_l2_link = sst.Link("l1_l2_link_" + str(x))
-    l1d_l2_link.connect( (l1d, "low_network_0", "50ps"), (l2, "high_network_0", "50ps") )
+    l1d_l2_link.connect( (l1d, "lowlink", "50ps"), (l2, "highlink", "50ps") )
 
     l2_bus_link = sst.Link("l2_bus_link_" + str(x))
-    l2_bus_link.connect( (l2, "low_network_0", "50ps"), (membus, "high_network_" + str(x), "50ps") )
+    l2_bus_link.connect( (l2, "lowlink", "50ps"), (membus, "highlink" + str(x), "50ps") )
 
 # Shared L3
 # 1MB*cores, 16-way set associative, 64B line, 15 cycle access
@@ -83,7 +83,7 @@
 } )
 
 l3_bus_link = sst.Link("l3_bus_link")
-l3_bus_link.connect( (l3, "high_network_0", "50ps"), (membus, "low_network_0", "50ps") )
+l3_bus_link.connect( (l3, "highlink", "50ps"), (membus, "lowlink0", "50ps") )
 
 # Memory/Controller
 # Using "simpleMem" memory model
@@ -97,6 +97,6 @@
 })
 
 memory_bus_link = sst.Link("memory_bus_link")
-memory_bus_link.connect( (l3, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") )
+memory_bus_link.connect( (l3, "lowlink", "50ps"), (memctrl, "highlink", "50ps") )
 
 print("Done configuring SST model")

src/sst/elements/ariel/frontend/simple/examples/opal/mlm_test.py

@@ -288,15 +288,18 @@
 }
 
 dc_params = {
-        "memNIC.interleave_size": str(mem_interleave_size) + "B",
-        "memNIC.interleave_step": str((groups * memory_controllers_per_group) * (mem_interleave_size)) + "B",
         "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize
         "clock": memory_clock,
-        "memNIC.network_bw": ring_bandwidth,
+        "interleave_size": str(mem_interleave_size) + "B",
+        "interleave_step": str((groups * memory_controllers_per_group) * (mem_interleave_size)) + "B",
         # Default params
 	# "coherence_protocol": coherence_protocol,
 }
 
+nic_params = {
+        "network_bw": ring_bandwidth,
+}
+
 router_map = {}
 
 print("Configuring Ring Network-on-Chip...")
@@ -340,9 +343,12 @@
 			l3cache.addParams({
 				"slice_id" : str(next_l3_cache_id)
        	    })
+            l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC")
+            l3_nic.addParams(nic_params)
+            l3_nic.addParam("group", 2)
 
 			l3_ring_link = sst.Link("l3_" + str(next_l3_cache_id) + "_link")
-			l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) )		
+			l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) )		
 
 			next_l3_cache_id = next_l3_cache_id + 1
 			next_network_id = next_network_id + 1
@@ -365,13 +371,17 @@
 			l2.addParams(l2_params)
 		else:
 			l2.addParams(l2_dummy_params)
+
+        l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC")
+        l2_nic.addParams(nic_params)
+        l2_nic.addParam("group", 1)
 
 		#l2.addParams(l2_prefetch_params)
 
 
 		'''
                 arielL1Link = sst.Link("cpu_cache_link_" + str(next_core_id))
-                arielL1Link.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency))
+                arielL1Link.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency))
 		arielL1Link.setNoCut()
 		'''
 
@@ -387,23 +397,23 @@
 		if next_core_id < cores_per_group*groups//2:
                 	arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency))
                 	ArielOpalLink.connect((ariel, "opal_link_%d"%next_core_id, ring_latency), (opal, "requestLink%d"%(next_core_id + cores_per_group*groups//2), ring_latency))
-                	MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency))
+                	MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency))
 			PTWOpalLink.connect( (mmu, "ptw_to_opal%d"%next_core_id, "50ps"), (opal, "requestLink%d"%next_core_id, "50ps") )
 			arielMMULink.setNoCut()
 			PTWOpalLink.setNoCut()
 			MMUCacheLink.setNoCut()
 		else:
-			PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core_id-cores_per_group*groups//2), ring_latency), (l1, "high_network_0", ring_latency))
+			PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core_id-cores_per_group*groups//2), ring_latency), (l1, "highlink", ring_latency))
 		#'''
 
 
 
 		l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link")
-       		l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency))				
+       		l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency))				
 		l2_core_link.setNoCut()
 
 		l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id))
-       		l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency))
+       		l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency))
 
 		next_network_id = next_network_id + 1
 		next_core_id = next_core_id + 1
@@ -417,9 +427,13 @@
 		l3cache.addParams({
 			"slice_id" : str(next_l3_cache_id)
      		})
+
+        l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC")
+        l3_nic.addParams(nic_params)
+        l3_nic.addParam("group", 2)
 
 		l3_ring_link = sst.Link("l3_" + str(next_l3_cache_id) + "_link")
-		l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) )		
+		l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) )		
 
 		next_l3_cache_id = next_l3_cache_id + 1
 		next_network_id = next_network_id + 1
@@ -429,6 +443,10 @@
 
 		mem = sst.Component("memory_" + str(next_memory_ctrl_id), "memHierarchy.MemController")
 		mem.addParams(mem_params)
+		mem.addParams({
+			"addr_range_start" : next_memory_ctrl_id * mem_interleave_size,
+			"addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size)
+		})
 
 		messier_inst = sst.Component("NVMmemory_" + str(next_memory_ctrl_id), "Messier")
 		messier_inst.addParams(messier_params)
@@ -439,17 +457,20 @@
 
 		dc = sst.Component("dc_" + str(next_memory_ctrl_id), "memHierarchy.DirectoryController")
 		dc.addParams({
-			"memNIC.addr_range_start" : next_memory_ctrl_id * mem_interleave_size,
-			"memNIC.addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size)
+			"addr_range_start" : next_memory_ctrl_id * mem_interleave_size,
+			"addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size)
 		})
 		dc.addParams(dc_params)
+        dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC")
+        dc_nic.addParams(nic_params)
+        dc_nic.addParam("group", 3)
 
 
 		memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id))
-		memLink.connect((mem, "direct_link", ring_latency), (dc, "memory", ring_latency))
+		memLink.connect((mem, "highlink", ring_latency), (dc, "lowlink", ring_latency))
 
 		netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id))
-		netLink.connect((dc, "network", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency))
+		netLink.connect((dc_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency))
 
 		next_network_id = next_network_id + 1
 		next_memory_ctrl_id = next_memory_ctrl_id + 1

src/sst/elements/ariel/frontend/simple/examples/stream/ariel_ivb.py

@@ -116,14 +116,15 @@
 
 dc_params = {
     "coherence_protocol": coherence_protocol,
-    "memNIC.network_bw": memory_network_bandwidth,
     "interleave_size": str(mem_interleave_size) + "B",
     "interleave_step": str((groups * memory_controllers_per_group) * mem_interleave_size) + "B",
     "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize
     "clock": memory_clock,
     "debug": 1,
 }
 
+nic_params = { "network_bw" : memory_network_bandwidth }
+
 print("Configuring Ariel processor model (" + str(groups * cores_per_group) + " cores)...")
 
 ariel = sst.Component("A0", "ariel.ariel")
@@ -186,15 +187,18 @@
         l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache")
         l2.addParams(l2_params)
         l2.addParams(l1_prefetch_params)
+        l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC")
+        l2_nic.addParams(nic_params)
+        l2_nic.addParam("group", 1)
 
         ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id))
-        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) )
+        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) )
 
         l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link")
-        l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency))
+        l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency))
 
         l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id))
-        l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
+        l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
 
         next_network_id = next_network_id + 1
         next_core_id = next_core_id + 1
@@ -209,15 +213,18 @@
         l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache")
         l2.addParams(l2_params)
         l2.addParams(l2_prefetch_params)
+        l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC")
+        l2_nic.addParams(nic_params)
+        l2_nic.addParam("group", 1)
 
         ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id))
-        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) )
+        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) )
 
         l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link")
-        l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency))
+        l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency))
 
         l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id))
-        l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
+        l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
 
         next_network_id = next_network_id + 1
         next_core_id = next_core_id + 1
@@ -231,9 +238,13 @@
         l3cache.addParams({
             "slice_id" : str((next_group * l3cache_blocks_per_group) + next_l3_cache_block)
         })
+
+        l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC")
+        l3_nic.addParams(nic_params)
+        l3_nic.addParam("group", 2)
 
         l3_ring_link = sst.Link("l3_ring_link_" + str((next_group * l3cache_blocks_per_group) + next_l3_cache_block))
-        l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) )
+        l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) )
 
         next_network_id = next_network_id + 1
 
@@ -255,12 +266,15 @@
             "addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size)
         })
         dc.addParams(dc_params)
+        dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC")
+        dc_nic.addParams(nic_params)
+        dc_nic.addParam("group", 3)
 
         memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id))
-        memLink.connect((memctrl, "direct_link", ring_latency), (dc, "memory", ring_latency))
+        memLink.connect((memctrl, "highlink", ring_latency), (dc, "lowlink", ring_latency))
 
         netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id))
-        netLink.connect((dc, "network", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
+        netLink.connect((dc_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
 
         next_network_id = next_network_id + 1
         next_memory_ctrl_id = next_memory_ctrl_id + 1

src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb.py

@@ -115,14 +115,17 @@
 
 dc_params = {
     "coherence_protocol": coherence_protocol,
-    "memNIC.network_bw": memory_network_bandwidth,
     "interleave_size": str(mem_interleave_size) + "B",
     "interleave_step": str((groups * memory_controllers_per_group) * mem_interleave_size) + "B",
     "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize
     "clock": memory_clock,
     "debug": 1,
 }
 
+nic_params = {
+    "network_bw": memory_network_bandwidth,
+    }
+
 print("Configuring Ariel processor model (" + str(groups * cores_per_group) + " cores)...")
 
 ariel = sst.Component("A0", "ariel.ariel")
@@ -182,15 +185,18 @@
         l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache")
         l2.addParams(l2_params)
         l2.addParams(l1_prefetch_params)
+        l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC")
+        l2_nic.addParams(nic_params)
+        l2_nic.addParam("group", 1)
 
         ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id))
-        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) )
+        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) )
 
         l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link")
-        l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency))
+        l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency))
 
         l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id))
-        l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
+        l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
 
         next_network_id = next_network_id + 1
         next_core_id = next_core_id + 1
@@ -205,15 +211,18 @@
         l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache")
         l2.addParams(l2_params)
         l2.addParams(l2_prefetch_params)
+        l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC")
+        l2_nic.addParams(nic_params)
+        l2_nic.addParam("group", 1)
 
         ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id))
-        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) )
+        ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) )
 
         l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link")
-        l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency))
+        l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency))
 
         l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id))
-        l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
+        l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
 
         next_network_id = next_network_id + 1
         next_core_id = next_core_id + 1
@@ -227,9 +236,12 @@
         l3cache.addParams({
             "slice_id" : str((next_group * l3cache_blocks_per_group) + next_l3_cache_block)
         })
+        l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC")
+        l3_nic.addParams(nic_params)
+        l3_nic.addParam("group", 2)
 
         l3_ring_link = sst.Link("l3_ring_link_" + str((next_group * l3cache_blocks_per_group) + next_l3_cache_block))
-        l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) )
+        l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) )
 
         next_network_id = next_network_id + 1
 
@@ -251,12 +263,15 @@
             "addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size)
         })
         dc.addParams(dc_params)
+        dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC")
+        dc_nic.addParams(nic_params)
+        dc_nic.addParam("group", 3)
 
         memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id))
-        memLink.connect((memctrl, "direct_link", ring_latency), (dc, "memory", ring_latency))
+        memLink.connect((memctrl, "highlink", ring_latency), (dc, "lowlink", ring_latency))
 
         netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id))
-        netLink.connect((dc, "network", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
+        netLink.connect((dc_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency))
 
         next_network_id = next_network_id + 1
         next_memory_ctrl_id = next_memory_ctrl_id + 1